276 lines
7.5 KiB
C
276 lines
7.5 KiB
C
/*****************************************************************************
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* McPAT
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2012 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#ifndef ARCH_CONST_H_
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#define ARCH_CONST_H_
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typedef struct{
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unsigned int capacity;
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unsigned int assoc;//fully
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unsigned int blocksize;
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} array_inputs;
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//Do Not change, unless you want to bypass the XML interface and do not care about the default values.
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//Global parameters
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const int number_of_cores = 8;
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const int number_of_L2s = 1;
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const int number_of_L3s = 1;
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const int number_of_NoCs = 1;
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const double archi_F_sz_nm = 90.0;
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const unsigned int dev_type = 0;
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const double CLOCKRATE = 1.2*1e9;
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const double AF = 0.5;
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//const bool inorder = true;
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const bool embedded = false; //NEW
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const bool homogeneous_cores = true;
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const bool temperature = 360;
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const int number_cache_levels = 3;
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const int L1_property = 0; //private 0; coherent 1, shared 2.
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const int L2_property = 2;
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const bool homogeneous_L2s = true;
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const bool L3_property = 2;
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const bool homogeneous_L3s = true;
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const double Max_area_deviation = 50;
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const double Max_dynamic_deviation =50; //New
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const int opt_dynamic_power = 1;
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const int opt_lakage_power = 0;
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const int opt_area = 0;
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const int interconnect_projection_type = 0;
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//******************************Core Parameters
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#if (inorder)
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const int opcode_length = 8;//Niagara
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const int reg_length = 5;//Niagara
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const int instruction_length = 32;//Niagara
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const int data_width = 64;
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#else
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const int opcode_length = 8;//16;//Niagara
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const int reg_length = 7;//Niagara
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const int instruction_length = 32;//Niagara
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const int data_width = 64;
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#endif
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//Caches
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//itlb
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const int itlbsize=512;
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const int itlbassoc=0;//fully
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const int itlbblocksize=8;
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//icache
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const int icachesize=32768;
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const int icacheassoc=4;
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const int icacheblocksize=32;
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//dtlb
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const int dtlbsize=512;
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const int dtlbassoc=0;//fully
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const int dtlbblocksize=8;
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//dcache
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const int dcachesize=32768;
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const int dcacheassoc=4;
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const int dcacheblocksize=32;
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const int dcache_write_buffers=8;
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//cache controllers
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//IB,
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const int numIBEntries = 64;
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const int IBsize = 64;//2*4*instruction_length/8*2;
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const int IBassoc = 0;//In Niagara it is still fully associ
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const int IBblocksize = 4;
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//IFB and MIL should have the same parameters CAM
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const int IFBsize=128;//
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const int IFBassoc=0;//In Niagara it is still fully associ
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const int IFBblocksize=4;
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const int icache_write_buffers=8;
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//register file RAM
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const int regfilesize=5760;
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const int regfileassoc=1;
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const int regfileblocksize=18;
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//regwin RAM
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const int regwinsize=256;
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const int regwinassoc=1;
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const int regwinblocksize=8;
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//store buffer, lsq
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const int lsqsize=512;
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const int lsqassoc=0;
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const int lsqblocksize=8;
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//data fill queue RAM
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const int dfqsize=1024;
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const int dfqassoc=1;
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const int dfqblocksize=16;
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//outside the cores
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//L2 cache bank
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const int l2cachesize=262144;
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const int l2cacheassoc=16;
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const int l2cacheblocksize=64;
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//L2 directory
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const int l2dirsize=1024;
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const int l2dirassoc=0;
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const int l2dirblocksize=2;
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//crossbar
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//PCX
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const int PCX_NUMBER_INPUT_PORTS_CROSSBAR = 8;
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const int PCX_NUMBER_OUTPUT_PORTS_CROSSBAR = 9;
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const int PCX_NUMBER_SIGNALS_PER_PORT_CROSSBAR =144;
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//PCX buffer RAM
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const int pcx_buffersize=1024;
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const int pcx_bufferassoc=1;
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const int pcx_bufferblocksize=32;
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const int pcx_numbuffer=5;
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//pcx arbiter
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const int pcx_arbsize=128;
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const int pcx_arbassoc=1;
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const int pcx_arbblocksize=2;
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const int pcx_numarb=5;
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//CPX
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const int CPX_NUMBER_INPUT_PORTS_CROSSBAR = 5;
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const int CPX_NUMBER_OUTPUT_PORTS_CROSSBAR = 8;
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const int CPX_NUMBER_SIGNALS_PER_PORT_CROSSBAR =150;
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//CPX buffer RAM
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const int cpx_buffersize=1024;
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const int cpx_bufferassoc=1;
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const int cpx_bufferblocksize=32;
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const int cpx_numbuffer=8;
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//cpx arbiter
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const int cpx_arbsize=128;
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const int cpx_arbassoc=1;
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const int cpx_arbblocksize=2;
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const int cpx_numarb=8;
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const int numPhysFloatRegs=256;
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const int numPhysIntRegs=32;
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const int numROBEntries=192;
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const int umRobs=1;
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const int BTBEntries=4096;
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const int BTBTagSize=16;
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const int LFSTSize=1024;
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const int LQEntries=32;
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const int RASSize=16;
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const int SQEntries=32;
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const int SSITSize=1024;
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const int activity=0;
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const int backComSize=5;
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const int cachePorts=200;
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const int choiceCtrBits=2;
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const int choicePredictorSize=8192;
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const int commitWidth=8;
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const int decodeWidth=8;
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const int dispatchWidth=8;
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const int fetchWidth=8;
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const int issueWidth=1;
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const int renameWidth=8;
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//what is this forwardComSize=5??
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const int globalCtrBits=2;
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const int globalHistoryBits=13;
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const int globalPredictorSize=8192;
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const int localCtrBits=2;
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const int localHistoryBits=11;
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const int localHistoryTableSize=2048;
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const int localPredictorSize=2048;
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const double Woutdrvnandn =30 *0.09;//(24.0 * LSCALE)
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const double Woutdrvnandp =12.5 *0.09;//(10.0 * LSCALE)
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const double Woutdrvnorn =7.5*0.09;//(6.0 * LSCALE)
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const double Woutdrvnorp =50 * 0.09;// (40.0 * LSCALE)
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const double Woutdrivern =60*0.09;//(48.0 * LSCALE)
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const double Woutdriverp =100 * 0.09;//(80.0 * LSCALE)
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/*
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smtCommitPolicy=RoundRobin
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smtFetchPolicy=SingleThread
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smtIQPolicy=Partitioned
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smtIQThreshold=100
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smtLSQPolicy=Partitioned
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smtLSQThreshold=100
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smtNumFetchingThreads=1
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smtROBPolicy=Partitioned
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smtROBThreshold=100
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squashWidth=8
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*/
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/*
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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repl=Null
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split=false
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split_size=0
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subblock_size=0
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tgts_per_mshr=20
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trace_addr=0
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two_queue=false
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cpu_side=system.cpu0.dcache_port
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mem_side=system.tol2bus.port[2]
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*/
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//[system.cpu0.dtb]
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//type=AlphaDT
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#endif /* ARCH_CONST_H_ */
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