Binh Pham b72c879868 o3: make dispatch LSQ full check more selective ... Dispatch should not check LSQ size/LSQ stall for non load/store instructions. This work was done while Binh was an intern at AMD Research.		2014-06-21 10:26:55 -07:00
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arch	style: eliminate equality tests with true and false	2014-05-31 18:00:23 -07:00
base	style: eliminate equality tests with true and false	2014-05-31 18:00:23 -07:00
cpu	o3: make dispatch LSQ full check more selective	2014-06-21 10:26:55 -07:00
dev	dev: Set HDLCD default pixel clock for 1080p @ 60Hz	2014-05-09 18:58:46 -04:00
doc	MEM: Put memory system document into doxygen	2012-09-25 11:49:41 -05:00
doxygen	MEM: Put memory system document into doxygen	2012-09-25 11:49:41 -05:00
kern	sim: Add openat/fstatat syscalls and fix mremap	2014-01-24 15:29:30 -06:00
mem	style: eliminate equality tests with true and false	2014-05-31 18:00:23 -07:00
proto	mem: Edit proto Packet and enhance the python script	2014-03-07 15:56:23 -05:00
python	cpu: Add flag name printing to StaticInst	2014-05-09 18:58:47 -04:00
sim	sim: More rigorous clocking comments	2014-06-09 22:01:16 -05:00
unittest	unittest: Fix build errors	2014-01-30 12:21:58 -06:00
Doxyfile	Doxygen: Update the version of the Doxyfile	2012-10-11 06:38:42 -04:00
SConscript	scons: Bump the compiler version to gcc 4.6 and clang 3.0	2014-06-10 17:44:39 -04:00