367 lines
41 KiB
Text
367 lines
41 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.525854 # Number of seconds simulated
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sim_ticks 525854475000 # Number of ticks simulated
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final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1224247 # Simulator instruction rate (inst/s)
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host_op_rate 1565155 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2360407719 # Simulator tick rate (ticks/s)
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host_mem_usage 233372 # Number of bytes of host memory used
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host_seconds 222.78 # Real time elapsed on the host
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sim_insts 272739291 # Number of instructions simulated
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sim_ops 348687131 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read 437312 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 167040 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 0 # Number of bytes written to this memory
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system.physmem.num_reads 6833 # Number of read requests responded to by this memory
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system.physmem.num_writes 0 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 831622 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 317654 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total 831622 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 191 # Number of system calls
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system.cpu.numCycles 1051708950 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 272739291 # Number of instructions committed
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system.cpu.committedOps 348687131 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 279584925 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
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system.cpu.num_func_calls 12433363 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 18102313 # number of instructions that are conditional controls
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system.cpu.num_int_insts 279584925 # number of integer instructions
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system.cpu.num_fp_insts 114216705 # number of float instructions
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system.cpu.num_int_register_reads 2212913209 # number of times the integer registers were read
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system.cpu.num_int_register_writes 251197915 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
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system.cpu.num_mem_refs 177024357 # number of memory refs
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system.cpu.num_load_insts 94648758 # Number of load instructions
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system.cpu.num_store_insts 82375599 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 1051708950 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 13796 # number of replacements
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system.cpu.icache.tagsinuse 1765.984158 # Cycle average of tags in use
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system.cpu.icache.total_refs 348644756 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 22344.725758 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 1765.984158 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.862297 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.862297 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 348644756 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 348644756 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 348644756 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 348644756 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 348644756 # number of overall hits
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system.cpu.icache.overall_hits::total 348644756 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
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system.cpu.icache.overall_misses::total 15603 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 328062000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 328062000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 328062000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 328062000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 328062000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 328062000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 348660359 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 348660359 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 348660359 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 348660359 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 348660359 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 348660359 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.572005 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281253000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 281253000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281253000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 281253000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281253000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 281253000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18025.572005 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 1332 # number of replacements
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system.cpu.dcache.tagsinuse 3078.396238 # Cycle average of tags in use
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system.cpu.dcache.total_refs 176641600 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 39446.538633 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 3078.396238 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.751562 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.751562 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 94570005 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 94570005 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
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system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
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system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
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system.cpu.dcache.demand_hits::cpu.data 176619810 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 176619810 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 176619810 # number of overall hits
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system.cpu.dcache.overall_hits::total 176619810 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses
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system.cpu.dcache.overall_misses::total 4478 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 79898000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 79898000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 160160000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 160160000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 240058000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 240058000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 240058000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 240058000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 94571611 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 94571611 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::cpu.data 176624288 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 176624288 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::cpu.data 176624288 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 176624288 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49749.688667 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55766.016713 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
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system.cpu.dcache.writebacks::total 998 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
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system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 48 # number of replacements
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system.cpu.l2cache.tagsinuse 3475.672922 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 13308 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 4883 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 2.725374 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 341.613272 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 2402.300580 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 731.759070 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.073312 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.022332 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.106069 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 12993 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 13232 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 12993 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 13248 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 12993 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 13248 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2610 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1367 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 3977 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2610 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 6833 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2610 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 6833 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135720000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 206804000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 135720000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 355316000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 135720000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 355316000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167276 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167276 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167276 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2610 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 3977 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2610 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 6833 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2610 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 6833 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104400000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159080000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104400000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 273320000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104400000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 273320000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|