1684 lines
194 KiB
Text
1684 lines
194 KiB
Text
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 2.582310 # Number of seconds simulated
|
|
sim_ticks 2582310281500 # Number of ticks simulated
|
|
final_tick 2582310281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 62666 # Simulator instruction rate (inst/s)
|
|
host_op_rate 80652 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 2566586582 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 395816 # Number of bytes of host memory used
|
|
host_seconds 1006.13 # Real time elapsed on the host
|
|
sim_insts 63050246 # Number of instructions simulated
|
|
sim_ops 81146063 # Number of ops (including micro ops) simulated
|
|
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.inst 396544 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.data 4372212 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.inst 425600 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.data 5220016 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 129953444 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu0.inst 396544 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu1.inst 425600 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 822144 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_written::writebacks 4241024 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::total 7270160 # Number of bytes written to this memory
|
|
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.inst 6196 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.data 68388 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.inst 6650 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.data 81589 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 15105053 # Number of read requests responded to by this memory
|
|
system.physmem.num_writes::writebacks 66266 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::total 823550 # Number of write requests responded to by this memory
|
|
system.physmem.bw_read::realview.clcd 46290976 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.dtb.walker 223 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.inst 153562 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.data 1693140 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.dtb.walker 273 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.inst 164814 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.data 2021452 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 50324488 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu0.inst 153562 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu1.inst 164814 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 318375 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::writebacks 1642337 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::cpu0.data 6583 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::cpu1.data 1166450 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::total 2815370 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::writebacks 1642337 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::realview.clcd 46290976 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.dtb.walker 223 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.inst 153562 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.data 1699723 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.dtb.walker 273 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.inst 164814 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.data 3187902 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 53139859 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu1.inst 320 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::cpu1.inst 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::cpu1.inst 124 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 149 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu1.inst 124 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 149 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s)
|
|
system.l2c.replacements 72453 # number of replacements
|
|
system.l2c.tagsinuse 52989.750711 # Cycle average of tags in use
|
|
system.l2c.total_refs 1967154 # Total number of references to valid blocks.
|
|
system.l2c.sampled_refs 137652 # Sample count of references to valid blocks.
|
|
system.l2c.avg_refs 14.290777 # Average number of references to valid blocks.
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.occ_blocks::writebacks 37689.434458 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.dtb.walker 3.667894 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.itb.walker 0.004429 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.inst 4220.453796 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.data 2953.326384 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu1.dtb.walker 6.708393 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu1.inst 4009.126872 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu1.data 4107.028485 # Average occupied blocks per requestor
|
|
system.l2c.occ_percent::writebacks 0.575095 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.dtb.walker 0.000056 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.inst 0.064399 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.data 0.045064 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.dtb.walker 0.000102 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.inst 0.061174 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.data 0.062668 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::total 0.808559 # Average percentage of cache occupancy
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 54491 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 6158 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 400629 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 165440 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 78380 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 6682 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 615050 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 201442 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1528272 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 583270 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 583270 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 1037 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 784 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 1821 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 208 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 159 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 367 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 48010 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 59262 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 107272 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 54491 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 6158 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 400629 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 213450 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 78380 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 6682 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 615050 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 260704 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1635544 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 54491 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 6158 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 400629 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 213450 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 78380 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 6682 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 615050 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 260704 # number of overall hits
|
|
system.l2c.overall_hits::total 1635544 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 9 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 6068 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 6301 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 6610 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 6328 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 25329 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 5681 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 4309 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 9990 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 780 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 578 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 1358 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 63459 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 76486 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 139945 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 9 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 6068 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 69760 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 6610 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 82814 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 165274 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 9 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 6068 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 69760 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 6610 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 82814 # number of overall misses
|
|
system.l2c.overall_misses::total 165274 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 470500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 112500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 323600498 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 331027497 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 573500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 351706500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 332606499 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 1340097494 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 20411497 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 27614499 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 48025996 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1617000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6615500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 8232500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 3380389982 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 4066537489 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 7446927471 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.dtb.walker 470500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.itb.walker 112500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 323600498 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 3711417479 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 573500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 351706500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 4399143988 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 8787024965 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.dtb.walker 470500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.itb.walker 112500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 323600498 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 3711417479 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 573500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 351706500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 4399143988 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 8787024965 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 54500 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 6160 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.inst 406697 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 171741 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 78391 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 6682 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 621660 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 207770 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 1553601 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 583270 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 583270 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 6718 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 5093 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 11811 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 988 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 737 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 1725 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 111469 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 135748 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 247217 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 54500 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 6160 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 406697 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 283210 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 78391 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 6682 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 621660 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 343518 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 1800818 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 54500 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 6160 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 406697 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 283210 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 78391 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 6682 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 621660 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 343518 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 1800818 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000165 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000325 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.014920 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.036689 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000140 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.010633 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.030457 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.016303 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.845639 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.846063 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.845822 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.789474 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.784261 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.787246 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.569297 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.563441 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.566082 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000165 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000325 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.014920 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.246319 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000140 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.010633 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.241076 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.091777 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000165 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000325 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.014920 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.246319 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000140 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.010633 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.241076 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.091777 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52277.777778 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 56250 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53329.020765 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52535.708142 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52136.363636 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53208.245083 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52561.077592 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 52907.635280 # average ReadReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3592.940855 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6408.563240 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 4807.407007 # average UpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2073.076923 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11445.501730 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 6062.223859 # average SCUpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53268.881987 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53167.082721 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 53213.244282 # average ReadExReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52277.777778 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 56250 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 53329.020765 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 53202.658816 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52136.363636 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 53208.245083 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 53120.776535 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 53166.408298 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52277.777778 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 56250 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 53329.020765 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 53202.658816 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52136.363636 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 53208.245083 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 53120.776535 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 53166.408298 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 66266 # number of writebacks
|
|
system.l2c.writebacks::total 66266 # number of writebacks
|
|
system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu1.inst 5 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu1.data 23 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.data 23 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.data 23 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 71 # number of overall MSHR hits
|
|
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 9 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.inst 6063 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.data 6263 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 6605 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.data 6305 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 25258 # number of ReadReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 5681 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 4309 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 9990 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 780 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 578 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 1358 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 63459 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 76486 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 139945 # number of ReadExReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.dtb.walker 9 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 6063 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 69722 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 6605 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 82791 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 165203 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.dtb.walker 9 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 6063 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 69722 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 6605 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 82791 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 165203 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 360000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 88000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 249380499 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 253173000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 440000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270856500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 254736000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 1029033999 # number of ReadReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 227403000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 172571500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 399974500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31217000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23131000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 54348000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2608915998 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3130662995 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 5739578993 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 360000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 88000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 249380499 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 2862088998 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 440000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 270856500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 3385398995 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 6768612992 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 360000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 88000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 249380499 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 2862088998 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 440000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 270856500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 3385398995 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 6768612992 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5579000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9186576500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2133500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122396919500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 131591208500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 704511999 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30785024883 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 31489536882 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5579000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9891088499 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2133500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 153181944383 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 163080745382 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000165 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000325 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014908 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036468 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000140 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030346 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.016258 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.845639 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.846063 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.845822 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.789474 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.784261 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.787246 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569297 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.563441 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.566082 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000165 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000325 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014908 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.246185 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000140 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.241009 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.091738 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000165 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000325 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014908 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.246185 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000140 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.241009 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.091738 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41131.535379 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40423.598914 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41007.797123 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40402.220460 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 40740.913730 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40028.692132 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40049.083314 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.487487 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40021.794872 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40019.031142 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40020.618557 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41111.835957 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40931.189956 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 41013.105098 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41131.535379 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41050.012880 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41007.797123 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40890.905956 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 40971.489573 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41131.535379 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41050.012880 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41007.797123 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40890.905956 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 40971.489573 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 9083896 # DTB read hits
|
|
system.cpu0.dtb.read_misses 37543 # DTB read misses
|
|
system.cpu0.dtb.write_hits 5286239 # DTB write hits
|
|
system.cpu0.dtb.write_misses 6882 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 2244 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 1393 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 382 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 574 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 9121439 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 5293121 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 14370135 # DTB hits
|
|
system.cpu0.dtb.misses 44425 # DTB misses
|
|
system.cpu0.dtb.accesses 14414560 # DTB accesses
|
|
system.cpu0.itb.inst_hits 4418601 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 6114 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 1409 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 1633 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 4424715 # ITB inst accesses
|
|
system.cpu0.itb.hits 4418601 # DTB hits
|
|
system.cpu0.itb.misses 6114 # DTB misses
|
|
system.cpu0.itb.accesses 4424715 # DTB accesses
|
|
system.cpu0.numCycles 66354055 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.BPredUnit.lookups 6346252 # Number of BP lookups
|
|
system.cpu0.BPredUnit.condPredicted 4857071 # Number of conditional branches predicted
|
|
system.cpu0.BPredUnit.condIncorrect 316053 # Number of conditional branches incorrect
|
|
system.cpu0.BPredUnit.BTBLookups 4075974 # Number of BTB lookups
|
|
system.cpu0.BPredUnit.BTBHits 3037671 # Number of BTB hits
|
|
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu0.BPredUnit.usedRAS 700378 # Number of times the RAS was used to get a target.
|
|
system.cpu0.BPredUnit.RASInCorrect 30829 # Number of incorrect RAS predictions.
|
|
system.cpu0.fetch.icacheStallCycles 12963003 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu0.fetch.Insts 33274045 # Number of instructions fetch has processed
|
|
system.cpu0.fetch.Branches 6346252 # Number of branches that fetch encountered
|
|
system.cpu0.fetch.predictedBranches 3738049 # Number of branches that fetch has predicted taken
|
|
system.cpu0.fetch.Cycles 7812188 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu0.fetch.SquashCycles 1602844 # Number of cycles fetch has spent squashing
|
|
system.cpu0.fetch.TlbCycles 89446 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu0.fetch.BlockedCycles 22023764 # Number of cycles fetch has spent blocked
|
|
system.cpu0.fetch.MiscStallCycles 5932 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu0.fetch.PendingTrapStallCycles 73578 # Number of stall cycles due to pending traps
|
|
system.cpu0.fetch.PendingQuiesceStallCycles 90886 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu0.fetch.IcacheWaitRetryStallCycles 179 # Number of stall cycles due to full MSHR
|
|
system.cpu0.fetch.CacheLines 4416774 # Number of cache lines fetched
|
|
system.cpu0.fetch.IcacheSquashes 175280 # Number of outstanding Icache misses that were squashed
|
|
system.cpu0.fetch.ItlbSquashes 3223 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu0.fetch.rateDist::samples 44209960 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::mean 0.971808 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::stdev 2.352806 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::0 36406101 82.35% 82.35% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::1 622907 1.41% 83.76% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::2 820090 1.85% 85.61% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::3 691511 1.56% 87.18% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::4 794774 1.80% 88.97% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::5 578673 1.31% 90.28% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::6 721468 1.63% 91.91% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::7 370773 0.84% 92.75% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::8 3203663 7.25% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::total 44209960 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.branchRate 0.095642 # Number of branch fetches per cycle
|
|
system.cpu0.fetch.rate 0.501462 # Number of inst fetches per cycle
|
|
system.cpu0.decode.IdleCycles 13460475 # Number of cycles decode is idle
|
|
system.cpu0.decode.BlockedCycles 22052761 # Number of cycles decode is blocked
|
|
system.cpu0.decode.RunCycles 7004876 # Number of cycles decode is running
|
|
system.cpu0.decode.UnblockCycles 606078 # Number of cycles decode is unblocking
|
|
system.cpu0.decode.SquashCycles 1085770 # Number of cycles decode is squashing
|
|
system.cpu0.decode.BranchResolved 992839 # Number of times decode resolved a branch
|
|
system.cpu0.decode.BranchMispred 66349 # Number of times decode detected a branch misprediction
|
|
system.cpu0.decode.DecodedInsts 41502146 # Number of instructions handled by decode
|
|
system.cpu0.decode.SquashedInsts 217622 # Number of squashed instructions handled by decode
|
|
system.cpu0.rename.SquashCycles 1085770 # Number of cycles rename is squashing
|
|
system.cpu0.rename.IdleCycles 14072541 # Number of cycles rename is idle
|
|
system.cpu0.rename.BlockCycles 6178049 # Number of cycles rename is blocking
|
|
system.cpu0.rename.serializeStallCycles 13569314 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RunCycles 6948288 # Number of cycles rename is running
|
|
system.cpu0.rename.UnblockCycles 2355998 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RenamedInsts 40249124 # Number of instructions processed by rename
|
|
system.cpu0.rename.ROBFullEvents 2572 # Number of times rename has blocked due to ROB full
|
|
system.cpu0.rename.IQFullEvents 473537 # Number of times rename has blocked due to IQ full
|
|
system.cpu0.rename.LSQFullEvents 1335703 # Number of times rename has blocked due to LSQ full
|
|
system.cpu0.rename.FullRegisterEvents 188 # Number of times there has been no free registers
|
|
system.cpu0.rename.RenamedOperands 40597200 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RenameLookups 181819083 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.int_rename_lookups 181783808 # Number of integer rename lookups
|
|
system.cpu0.rename.fp_rename_lookups 35275 # Number of floating rename lookups
|
|
system.cpu0.rename.CommittedMaps 31678350 # Number of HB maps that are committed
|
|
system.cpu0.rename.UndoneMaps 8918849 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.serializingInsts 463403 # count of serializing insts renamed
|
|
system.cpu0.rename.tempSerializingInsts 418800 # count of temporary serializing insts renamed
|
|
system.cpu0.rename.skidInsts 5692374 # count of insts added to the skid buffer
|
|
system.cpu0.memDep0.insertedLoads 7927385 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 5883720 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.conflictingLoads 1132627 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 1230816 # Number of conflicting stores.
|
|
system.cpu0.iq.iqInstsAdded 38008933 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqNonSpecInstsAdded 947103 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqInstsIssued 38247071 # Number of instructions issued
|
|
system.cpu0.iq.iqSquashedInstsIssued 93468 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedInstsExamined 6756686 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedOperandsExamined 14324325 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 258267 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.issued_per_cycle::samples 44209960 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::mean 0.865123 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::stdev 1.479533 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::0 28324155 64.07% 64.07% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::1 6346765 14.36% 78.42% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::2 3236431 7.32% 85.74% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::3 2507997 5.67% 91.42% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::4 2107881 4.77% 96.18% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::5 937016 2.12% 98.30% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::6 515116 1.17% 99.47% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::7 180639 0.41% 99.88% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::8 53960 0.12% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::total 44209960 # Number of insts issued each cycle
|
|
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntAlu 27715 2.59% 2.59% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntMult 460 0.04% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemRead 839091 78.45% 81.09% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemWrite 202283 18.91% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntAlu 22968400 60.05% 60.19% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntMult 50115 0.13% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShiftAcc 11 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemRead 9563149 25.00% 85.33% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemWrite 5612341 14.67% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::total 38247071 # Type of FU issued
|
|
system.cpu0.iq.rate 0.576409 # Inst issue rate
|
|
system.cpu0.iq.fu_busy_cnt 1069549 # FU busy when requested
|
|
system.cpu0.iq.fu_busy_rate 0.027964 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.int_inst_queue_reads 121902835 # Number of integer instruction queue reads
|
|
system.cpu0.iq.int_inst_queue_writes 45721169 # Number of integer instruction queue writes
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 35306324 # Number of integer instruction queue wakeup accesses
|
|
system.cpu0.iq.fp_inst_queue_reads 8427 # Number of floating instruction queue reads
|
|
system.cpu0.iq.fp_inst_queue_writes 4840 # Number of floating instruction queue writes
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 3930 # Number of floating instruction queue wakeup accesses
|
|
system.cpu0.iq.int_alu_accesses 39259896 # Number of integer alu accesses
|
|
system.cpu0.iq.fp_alu_accesses 4380 # Number of floating point alu accesses
|
|
system.cpu0.iew.lsq.thread0.forwLoads 325721 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 1504145 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 3982 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 13879 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread0.squashedStores 608088 # Number of stores squashed
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 2149487 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 5263 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewSquashCycles 1085770 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewBlockCycles 4069341 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewUnblockCycles 129560 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.iewDispatchedInsts 39094255 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewDispSquashedInsts 87678 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispLoadInsts 7927385 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispStoreInsts 5883720 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 614122 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewIQFullEvents 49261 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewLSQFullEvents 17662 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.memOrderViolationEvents 13879 # Number of memory order violations
|
|
system.cpu0.iew.predictedTakenIncorrect 160370 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.iew.predictedNotTakenIncorrect 144551 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.branchMispredicts 304921 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewExecutedInsts 37828601 # Number of executed instructions
|
|
system.cpu0.iew.iewExecLoadInsts 9401576 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 418470 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu0.iew.exec_nop 138219 # number of nop insts executed
|
|
system.cpu0.iew.exec_refs 14960222 # number of memory reference insts executed
|
|
system.cpu0.iew.exec_branches 5069889 # Number of branches executed
|
|
system.cpu0.iew.exec_stores 5558646 # Number of stores executed
|
|
system.cpu0.iew.exec_rate 0.570102 # Inst execution rate
|
|
system.cpu0.iew.wb_sent 37608832 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.wb_count 35310254 # cumulative count of insts written-back
|
|
system.cpu0.iew.wb_producers 18670977 # num instructions producing a value
|
|
system.cpu0.iew.wb_consumers 35573590 # num instructions consuming a value
|
|
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu0.iew.wb_rate 0.532149 # insts written-back per cycle
|
|
system.cpu0.iew.wb_fanout 0.524855 # average fanout of values written-back
|
|
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu0.commit.commitCommittedInsts 24262280 # The number of committed instructions
|
|
system.cpu0.commit.commitCommittedOps 31997725 # The number of committed instructions
|
|
system.cpu0.commit.commitSquashedInsts 6679991 # The number of squashed insts skipped by commit
|
|
system.cpu0.commit.commitNonSpecStalls 688836 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu0.commit.branchMispredicts 267429 # The number of times a branch was mispredicted
|
|
system.cpu0.commit.committed_per_cycle::samples 43160582 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::mean 0.741365 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::stdev 1.695624 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::0 31020137 71.87% 71.87% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::1 6071618 14.07% 85.94% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::2 1950463 4.52% 90.46% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::3 1036843 2.40% 92.86% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::4 799662 1.85% 94.71% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::5 507487 1.18% 95.89% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::6 407135 0.94% 96.83% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::7 202137 0.47% 97.30% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::8 1165100 2.70% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::total 43160582 # Number of insts commited each cycle
|
|
system.cpu0.commit.committedInsts 24262280 # Number of instructions committed
|
|
system.cpu0.commit.committedOps 31997725 # Number of ops (including micro ops) committed
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu0.commit.refs 11698872 # Number of memory references committed
|
|
system.cpu0.commit.loads 6423240 # Number of loads committed
|
|
system.cpu0.commit.membars 234547 # Number of memory barriers committed
|
|
system.cpu0.commit.branches 4415502 # Number of branches committed
|
|
system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
|
|
system.cpu0.commit.int_insts 28265931 # Number of committed integer instructions.
|
|
system.cpu0.commit.function_calls 499946 # Number of function calls committed.
|
|
system.cpu0.commit.bw_lim_events 1165100 # number cycles where commit BW limit reached
|
|
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu0.rob.rob_reads 79788976 # The number of ROB reads
|
|
system.cpu0.rob.rob_writes 78443760 # The number of ROB writes
|
|
system.cpu0.timesIdled 426851 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.idleCycles 22144095 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.quiesceCycles 5098222727 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu0.committedInsts 24181538 # Number of Instructions Simulated
|
|
system.cpu0.committedOps 31916983 # Number of Ops (including micro ops) Simulated
|
|
system.cpu0.committedInsts_total 24181538 # Number of Instructions Simulated
|
|
system.cpu0.cpi 2.743996 # CPI: Cycles Per Instruction
|
|
system.cpu0.cpi_total 2.743996 # CPI: Total CPI of All Threads
|
|
system.cpu0.ipc 0.364432 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 0.364432 # IPC: Total IPC of All Threads
|
|
system.cpu0.int_regfile_reads 176533858 # number of integer regfile reads
|
|
system.cpu0.int_regfile_writes 35079827 # number of integer regfile writes
|
|
system.cpu0.fp_regfile_reads 3404 # number of floating regfile reads
|
|
system.cpu0.fp_regfile_writes 942 # number of floating regfile writes
|
|
system.cpu0.misc_regfile_reads 47584444 # number of misc regfile reads
|
|
system.cpu0.misc_regfile_writes 527516 # number of misc regfile writes
|
|
system.cpu0.icache.replacements 406873 # number of replacements
|
|
system.cpu0.icache.tagsinuse 511.614484 # Cycle average of tags in use
|
|
system.cpu0.icache.total_refs 3975135 # Total number of references to valid blocks.
|
|
system.cpu0.icache.sampled_refs 407385 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.avg_refs 9.757686 # Average number of references to valid blocks.
|
|
system.cpu0.icache.warmup_cycle 6470209000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.occ_blocks::cpu0.inst 511.614484 # Average occupied blocks per requestor
|
|
system.cpu0.icache.occ_percent::cpu0.inst 0.999247 # Average percentage of cache occupancy
|
|
system.cpu0.icache.occ_percent::total 0.999247 # Average percentage of cache occupancy
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 3975135 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 3975135 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 3975135 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 3975135 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 3975135 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 3975135 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 441500 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 441500 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 441500 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 441500 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 441500 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 441500 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7129067996 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 7129067996 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 7129067996 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 7129067996 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 7129067996 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 7129067996 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 4416635 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 4416635 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 4416635 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 4416635 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 4416635 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 4416635 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099963 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.099963 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099963 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.099963 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099963 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.099963 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16147.379379 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 16147.379379 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16147.379379 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 16147.379379 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16147.379379 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 16147.379379 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 1348496 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 167 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 8074.826347 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 34106 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 34106 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 34106 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 34106 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 34106 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 34106 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407394 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 407394 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 407394 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 407394 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 407394 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 407394 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5468654996 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 5468654996 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5468654996 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 5468654996 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5468654996 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 5468654996 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8379000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8379000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8379000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 8379000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092241 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092241 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092241 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.092241 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092241 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.092241 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13423.504018 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13423.504018 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13423.504018 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13423.504018 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13423.504018 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13423.504018 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.replacements 275592 # number of replacements
|
|
system.cpu0.dcache.tagsinuse 476.837382 # Cycle average of tags in use
|
|
system.cpu0.dcache.total_refs 9554493 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.sampled_refs 276104 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.avg_refs 34.604689 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.warmup_cycle 51448000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.occ_blocks::cpu0.data 476.837382 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.occ_percent::cpu0.data 0.931323 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.occ_percent::total 0.931323 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 5935954 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 5935954 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 3226635 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 3226635 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174405 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 174405 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171548 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 171548 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 9162589 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 9162589 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 9162589 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 9162589 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 400527 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 400527 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 1594104 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 1594104 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8985 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 8985 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7776 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 7776 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 1994631 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 1994631 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 1994631 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 1994631 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7261400500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 7261400500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71837415855 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 71837415855 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 113971500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 113971500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 93410500 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 93410500 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 79098816355 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 79098816355 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 79098816355 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 79098816355 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6336481 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 6336481 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4820739 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 4820739 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183390 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 183390 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179324 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 179324 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 11157220 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 11157220 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 11157220 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 11157220 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063210 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.063210 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330676 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.330676 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048994 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048994 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043363 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043363 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178775 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.178775 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178775 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.178775 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18129.615482 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 18129.615482 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45064.447398 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 45064.447398 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12684.641068 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12684.641068 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12012.667181 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12012.667181 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39655.864345 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 39655.864345 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39655.864345 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 39655.864345 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 7527492 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 1548500 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 1462 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 87 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 5148.763338 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 17798.850575 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 255542 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 255542 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211236 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 211236 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1463026 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 1463026 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 516 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 516 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1674262 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 1674262 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1674262 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 1674262 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189291 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 189291 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131078 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 131078 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8469 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8469 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7773 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7773 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 320369 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 320369 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 320369 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 320369 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2800937917 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2800937917 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4685815512 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4685815512 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79569505 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79569505 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 68924555 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 68924555 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7486753429 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 7486753429 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7486753429 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 7486753429 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10315126500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10315126500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 849486399 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 849486399 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11164612899 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11164612899 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029873 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029873 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027190 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027190 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046180 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046180 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043346 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043346 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028714 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.028714 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028714 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.028714 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14796.994664 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14796.994664 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35748.298814 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35748.298814 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9395.383753 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9395.383753 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8867.175479 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8867.175479 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23369.156907 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23369.156907 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23369.156907 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23369.156907 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 43445270 # DTB read hits
|
|
system.cpu1.dtb.read_misses 46285 # DTB read misses
|
|
system.cpu1.dtb.write_hits 7088572 # DTB write hits
|
|
system.cpu1.dtb.write_misses 12217 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 2504 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 3688 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 371 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 674 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 43491555 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 7100789 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 50533842 # DTB hits
|
|
system.cpu1.dtb.misses 58502 # DTB misses
|
|
system.cpu1.dtb.accesses 50592344 # DTB accesses
|
|
system.cpu1.itb.inst_hits 9223213 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 6180 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 1615 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 1780 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 9229393 # ITB inst accesses
|
|
system.cpu1.itb.hits 9223213 # DTB hits
|
|
system.cpu1.itb.misses 6180 # DTB misses
|
|
system.cpu1.itb.accesses 9229393 # DTB accesses
|
|
system.cpu1.numCycles 355232424 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.BPredUnit.lookups 9848764 # Number of BP lookups
|
|
system.cpu1.BPredUnit.condPredicted 8083275 # Number of conditional branches predicted
|
|
system.cpu1.BPredUnit.condIncorrect 447123 # Number of conditional branches incorrect
|
|
system.cpu1.BPredUnit.BTBLookups 6868345 # Number of BTB lookups
|
|
system.cpu1.BPredUnit.BTBHits 5662939 # Number of BTB hits
|
|
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.BPredUnit.usedRAS 832004 # Number of times the RAS was used to get a target.
|
|
system.cpu1.BPredUnit.RASInCorrect 49676 # Number of incorrect RAS predictions.
|
|
system.cpu1.fetch.icacheStallCycles 22148379 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.Insts 71952458 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.Branches 9848764 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.predictedBranches 6494943 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.Cycles 15333431 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.SquashCycles 4632908 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.TlbCycles 88364 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu1.fetch.BlockedCycles 74838070 # Number of cycles fetch has spent blocked
|
|
system.cpu1.fetch.MiscStallCycles 5775 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.PendingTrapStallCycles 63991 # Number of stall cycles due to pending traps
|
|
system.cpu1.fetch.PendingQuiesceStallCycles 141562 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu1.fetch.IcacheWaitRetryStallCycles 138 # Number of stall cycles due to full MSHR
|
|
system.cpu1.fetch.CacheLines 9221022 # Number of cache lines fetched
|
|
system.cpu1.fetch.IcacheSquashes 859641 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.ItlbSquashes 3677 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu1.fetch.rateDist::samples 115781579 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 0.750934 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 2.109459 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 100456410 86.76% 86.76% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 829573 0.72% 87.48% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 1015846 0.88% 88.36% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 2061622 1.78% 90.14% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 1645380 1.42% 91.56% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 616095 0.53% 92.09% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 2274849 1.96% 94.06% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 467300 0.40% 94.46% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 6414504 5.54% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 115781579 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.branchRate 0.027725 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.rate 0.202550 # Number of inst fetches per cycle
|
|
system.cpu1.decode.IdleCycles 23776389 # Number of cycles decode is idle
|
|
system.cpu1.decode.BlockedCycles 74601447 # Number of cycles decode is blocked
|
|
system.cpu1.decode.RunCycles 13781615 # Number of cycles decode is running
|
|
system.cpu1.decode.UnblockCycles 561009 # Number of cycles decode is unblocking
|
|
system.cpu1.decode.SquashCycles 3061119 # Number of cycles decode is squashing
|
|
system.cpu1.decode.BranchResolved 1241407 # Number of times decode resolved a branch
|
|
system.cpu1.decode.BranchMispred 102665 # Number of times decode detected a branch misprediction
|
|
system.cpu1.decode.DecodedInsts 81190791 # Number of instructions handled by decode
|
|
system.cpu1.decode.SquashedInsts 341149 # Number of squashed instructions handled by decode
|
|
system.cpu1.rename.SquashCycles 3061119 # Number of cycles rename is squashing
|
|
system.cpu1.rename.IdleCycles 25333003 # Number of cycles rename is idle
|
|
system.cpu1.rename.BlockCycles 33967991 # Number of cycles rename is blocking
|
|
system.cpu1.rename.serializeStallCycles 36116187 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RunCycles 12703540 # Number of cycles rename is running
|
|
system.cpu1.rename.UnblockCycles 4599739 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RenamedInsts 74711209 # Number of instructions processed by rename
|
|
system.cpu1.rename.ROBFullEvents 20422 # Number of times rename has blocked due to ROB full
|
|
system.cpu1.rename.IQFullEvents 719883 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.LSQFullEvents 3284162 # Number of times rename has blocked due to LSQ full
|
|
system.cpu1.rename.FullRegisterEvents 33659 # Number of times there has been no free registers
|
|
system.cpu1.rename.RenamedOperands 79078972 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RenameLookups 344223554 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.int_rename_lookups 344164086 # Number of integer rename lookups
|
|
system.cpu1.rename.fp_rename_lookups 59468 # Number of floating rename lookups
|
|
system.cpu1.rename.CommittedMaps 50180386 # Number of HB maps that are committed
|
|
system.cpu1.rename.UndoneMaps 28898586 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.serializingInsts 486916 # count of serializing insts renamed
|
|
system.cpu1.rename.tempSerializingInsts 421354 # count of temporary serializing insts renamed
|
|
system.cpu1.rename.skidInsts 8389500 # count of insts added to the skid buffer
|
|
system.cpu1.memDep0.insertedLoads 14026564 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 8607423 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.conflictingLoads 1068694 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 1518812 # Number of conflicting stores.
|
|
system.cpu1.iq.iqInstsAdded 67421543 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqNonSpecInstsAdded 1209489 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqInstsIssued 91958955 # Number of instructions issued
|
|
system.cpu1.iq.iqSquashedInstsIssued 109721 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedInstsExamined 18898752 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedOperandsExamined 53543776 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 290002 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.issued_per_cycle::samples 115781579 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::mean 0.794245 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::stdev 1.521941 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::0 83973534 72.53% 72.53% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::1 9124499 7.88% 80.41% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::2 4576997 3.95% 84.36% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::3 4009566 3.46% 87.82% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::4 10699106 9.24% 97.07% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::5 1974757 1.71% 98.77% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::6 1060771 0.92% 99.69% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::7 281863 0.24% 99.93% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::8 80486 0.07% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::total 115781579 # Number of insts issued each cycle
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntAlu 29310 0.37% 0.37% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntMult 993 0.01% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemRead 7573445 95.84% 96.23% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemWrite 298199 3.77% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.FU_type_0::No_OpClass 313737 0.34% 0.34% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntAlu 39470238 42.92% 43.26% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntMult 61477 0.07% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 1690 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.33% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemRead 44643108 48.55% 91.88% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemWrite 7468676 8.12% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::total 91958955 # Type of FU issued
|
|
system.cpu1.iq.rate 0.258870 # Inst issue rate
|
|
system.cpu1.iq.fu_busy_cnt 7901947 # FU busy when requested
|
|
system.cpu1.iq.fu_busy_rate 0.085929 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.int_inst_queue_reads 307754751 # Number of integer instruction queue reads
|
|
system.cpu1.iq.int_inst_queue_writes 87542996 # Number of integer instruction queue writes
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 55769663 # Number of integer instruction queue wakeup accesses
|
|
system.cpu1.iq.fp_inst_queue_reads 14772 # Number of floating instruction queue reads
|
|
system.cpu1.iq.fp_inst_queue_writes 8137 # Number of floating instruction queue writes
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 6817 # Number of floating instruction queue wakeup accesses
|
|
system.cpu1.iq.int_alu_accesses 99539441 # Number of integer alu accesses
|
|
system.cpu1.iq.fp_alu_accesses 7724 # Number of floating point alu accesses
|
|
system.cpu1.iew.lsq.thread0.forwLoads 371642 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 4037130 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 6814 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 21954 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread0.squashedStores 1589436 # Number of stores squashed
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 31965709 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 1043610 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewSquashCycles 3061119 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewBlockCycles 25601852 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewUnblockCycles 406330 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.iewDispatchedInsts 68756671 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewDispSquashedInsts 131432 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispLoadInsts 14026564 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispStoreInsts 8607423 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 899609 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewIQFullEvents 81519 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewLSQFullEvents 7124 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.memOrderViolationEvents 21954 # Number of memory order violations
|
|
system.cpu1.iew.predictedTakenIncorrect 226065 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.iew.predictedNotTakenIncorrect 196785 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.branchMispredicts 422850 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewExecutedInsts 89098857 # Number of executed instructions
|
|
system.cpu1.iew.iewExecLoadInsts 43830249 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 2860098 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu1.iew.exec_nop 125639 # number of nop insts executed
|
|
system.cpu1.iew.exec_refs 51224079 # number of memory reference insts executed
|
|
system.cpu1.iew.exec_branches 7396455 # Number of branches executed
|
|
system.cpu1.iew.exec_stores 7393830 # Number of stores executed
|
|
system.cpu1.iew.exec_rate 0.250818 # Inst execution rate
|
|
system.cpu1.iew.wb_sent 87931251 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.wb_count 55776480 # cumulative count of insts written-back
|
|
system.cpu1.iew.wb_producers 30792122 # num instructions producing a value
|
|
system.cpu1.iew.wb_consumers 54566321 # num instructions consuming a value
|
|
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.wb_rate 0.157014 # insts written-back per cycle
|
|
system.cpu1.iew.wb_fanout 0.564306 # average fanout of values written-back
|
|
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.commit.commitCommittedInsts 38938347 # The number of committed instructions
|
|
system.cpu1.commit.commitCommittedOps 49298719 # The number of committed instructions
|
|
system.cpu1.commit.commitSquashedInsts 19014978 # The number of squashed insts skipped by commit
|
|
system.cpu1.commit.commitNonSpecStalls 919487 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.branchMispredicts 376070 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.committed_per_cycle::samples 112768879 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::mean 0.437166 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::stdev 1.403258 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::0 95484340 84.67% 84.67% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::1 8537208 7.57% 92.24% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::2 2210726 1.96% 94.20% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::3 1312266 1.16% 95.37% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::4 1283048 1.14% 96.50% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::5 588048 0.52% 97.03% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::6 1003635 0.89% 97.92% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::7 487845 0.43% 98.35% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::8 1861763 1.65% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::total 112768879 # Number of insts commited each cycle
|
|
system.cpu1.commit.committedInsts 38938347 # Number of instructions committed
|
|
system.cpu1.commit.committedOps 49298719 # Number of ops (including micro ops) committed
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.refs 17007421 # Number of memory references committed
|
|
system.cpu1.commit.loads 9989434 # Number of loads committed
|
|
system.cpu1.commit.membars 202281 # Number of memory barriers committed
|
|
system.cpu1.commit.branches 6220621 # Number of branches committed
|
|
system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
|
|
system.cpu1.commit.int_insts 43690243 # Number of committed integer instructions.
|
|
system.cpu1.commit.function_calls 556165 # Number of function calls committed.
|
|
system.cpu1.commit.bw_lim_events 1861763 # number cycles where commit BW limit reached
|
|
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu1.rob.rob_reads 178106600 # The number of ROB reads
|
|
system.cpu1.rob.rob_writes 139781050 # The number of ROB writes
|
|
system.cpu1.timesIdled 1519184 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.idleCycles 239450845 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.quiesceCycles 4808685831 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu1.committedInsts 38868708 # Number of Instructions Simulated
|
|
system.cpu1.committedOps 49229080 # Number of Ops (including micro ops) Simulated
|
|
system.cpu1.committedInsts_total 38868708 # Number of Instructions Simulated
|
|
system.cpu1.cpi 9.139291 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 9.139291 # CPI: Total CPI of All Threads
|
|
system.cpu1.ipc 0.109418 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 0.109418 # IPC: Total IPC of All Threads
|
|
system.cpu1.int_regfile_reads 398713179 # number of integer regfile reads
|
|
system.cpu1.int_regfile_writes 58485097 # number of integer regfile writes
|
|
system.cpu1.fp_regfile_reads 4918 # number of floating regfile reads
|
|
system.cpu1.fp_regfile_writes 2338 # number of floating regfile writes
|
|
system.cpu1.misc_regfile_reads 91819776 # number of misc regfile reads
|
|
system.cpu1.misc_regfile_writes 429481 # number of misc regfile writes
|
|
system.cpu1.icache.replacements 621812 # number of replacements
|
|
system.cpu1.icache.tagsinuse 498.762593 # Cycle average of tags in use
|
|
system.cpu1.icache.total_refs 8548797 # Total number of references to valid blocks.
|
|
system.cpu1.icache.sampled_refs 622324 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.avg_refs 13.736891 # Average number of references to valid blocks.
|
|
system.cpu1.icache.warmup_cycle 74633258000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.occ_blocks::cpu1.inst 498.762593 # Average occupied blocks per requestor
|
|
system.cpu1.icache.occ_percent::cpu1.inst 0.974146 # Average percentage of cache occupancy
|
|
system.cpu1.icache.occ_percent::total 0.974146 # Average percentage of cache occupancy
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 8548797 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 8548797 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 8548797 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 8548797 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 8548797 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 8548797 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 672174 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 672174 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 672174 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 672174 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 672174 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 672174 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10613540997 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 10613540997 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 10613540997 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 10613540997 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 10613540997 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 10613540997 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 9220971 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 9220971 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 9220971 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 9220971 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 9220971 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 9220971 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.072896 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.072896 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.072896 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.072896 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.072896 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.072896 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15789.871368 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 15789.871368 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15789.871368 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 15789.871368 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15789.871368 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 15789.871368 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 1180997 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 198 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs 5964.631313 # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 49820 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_hits::total 49820 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::cpu1.inst 49820 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::total 49820 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::cpu1.inst 49820 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::total 49820 # number of overall MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622354 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 622354 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 622354 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 622354 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 622354 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 622354 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8128418498 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 8128418498 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8128418498 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 8128418498 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8128418498 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 8128418498 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3154000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3154000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3154000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::total 3154000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067493 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067493 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067493 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.067493 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067493 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.067493 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13060.763646 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13060.763646 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13060.763646 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13060.763646 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13060.763646 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13060.763646 # average overall mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.replacements 362958 # number of replacements
|
|
system.cpu1.dcache.tagsinuse 487.094495 # Cycle average of tags in use
|
|
system.cpu1.dcache.total_refs 13107479 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.sampled_refs 363304 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.avg_refs 36.078543 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.warmup_cycle 70482639000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.occ_blocks::cpu1.data 487.094495 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.occ_percent::cpu1.data 0.951356 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.occ_percent::total 0.951356 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 8608268 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 8608268 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 4252418 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 4252418 # number of WriteReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 106100 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 106100 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100714 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 100714 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 12860686 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 12860686 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 12860686 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 12860686 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 410615 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 410615 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 1595619 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 1595619 # number of WriteReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14222 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 14222 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10905 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 10905 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 2006234 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 2006234 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 2006234 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 2006234 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8133768000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 8133768000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66485489237 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 66485489237 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 165213500 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 165213500 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 94467000 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 94467000 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 74619257237 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 74619257237 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 74619257237 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 74619257237 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 9018883 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 9018883 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 5848037 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 5848037 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 120322 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 120322 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111619 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 111619 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 14866920 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 14866920 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 14866920 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 14866920 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045528 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.045528 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.272847 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.272847 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118199 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118199 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097698 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097698 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134946 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.134946 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134946 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.134946 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19808.745418 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 19808.745418 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41667.521656 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 41667.521656 # average WriteReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11616.755731 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11616.755731 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8662.723521 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8662.723521 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 37193.695868 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 37193.695868 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 37193.695868 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 37193.695868 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 29476015 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 5620000 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 6671 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 172 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4418.530205 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets 32674.418605 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 327729 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 327729 # number of writebacks
|
|
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 179332 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_hits::total 179332 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432824 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::total 1432824 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1447 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::cpu1.data 1612156 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::total 1612156 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::cpu1.data 1612156 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::total 1612156 # number of overall MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231283 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 231283 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162795 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 162795 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12775 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12775 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10900 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 10900 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 394078 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 394078 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 394078 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 394078 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3556387454 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3556387454 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5557887685 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5557887685 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 103446504 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 103446504 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60421505 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60421505 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9114275139 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 9114275139 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9114275139 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 9114275139 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137004022500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137004022500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40580989302 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40580989302 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 177585011802 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 177585011802 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025644 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025644 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027838 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027838 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106173 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106173 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097654 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097654 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.026507 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.026507 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15376.778466 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15376.778466 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34140.407783 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34140.407783 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8097.573699 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8097.573699 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5543.257339 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5543.257339 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23128.099359 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23128.099359 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23128.099359 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23128.099359 # average overall mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.replacements 0 # number of replacements
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305599683923 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 1305599683923 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305599683923 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 1305599683923 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 43782 # number of quiesce instructions executed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 53899 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|