74553c7d3f
This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
392 lines
45 KiB
Text
392 lines
45 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000028 # Number of seconds simulated
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sim_ticks 27800000 # Number of ticks simulated
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final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 413138 # Simulator instruction rate (inst/s)
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host_op_rate 412367 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2148212772 # Simulator tick rate (ticks/s)
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host_mem_usage 231400 # Number of bytes of host memory used
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host_seconds 0.01 # Real time elapsed on the host
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sim_insts 5327 # Number of instructions simulated
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sim_ops 5327 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
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system.physmem.bytes_read::total 24896 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 389 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 587050360 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 308489209 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 895539568 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 587050360 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 587050360 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 895539568 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 308 # Transaction distribution
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system.membus.trans_dist::ReadResp 308 # Transaction distribution
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system.membus.trans_dist::ReadExReq 81 # Transaction distribution
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system.membus.trans_dist::ReadExResp 81 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side 778 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count 778 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 24896 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size 24896 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 24896 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
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system.membus.respLayer1.occupancy 3501000 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 12.6 # Layer utilization (%)
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system.cpu.workload.num_syscalls 11 # Number of system calls
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system.cpu.numCycles 55600 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 5327 # Number of instructions committed
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system.cpu.committedOps 5327 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_func_calls 146 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls
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system.cpu.num_int_insts 4505 # number of integer instructions
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system.cpu.num_fp_insts 0 # number of float instructions
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system.cpu.num_int_register_reads 10598 # number of times the integer registers were read
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system.cpu.num_int_register_writes 4845 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 1401 # number of memory refs
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system.cpu.num_load_insts 723 # Number of load instructions
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system.cpu.num_store_insts 678 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 55600 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.tagsinuse 117.043638 # Cycle average of tags in use
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system.cpu.icache.total_refs 5114 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 19.898833 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.057150 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 5114 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 5114 # number of overall hits
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system.cpu.icache.overall_hits::total 5114 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses
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system.cpu.icache.overall_misses::total 257 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 14051000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 14051000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 14051000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 14051000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 14051000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 5371 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 5371 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 5371 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047850 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.047850 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54673.151751 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 54673.151751 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 54673.151751 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 54673.151751 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 257 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13537000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 13537000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13537000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 13537000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13537000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 13537000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.tagsinuse 142.183999 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::total 0.004339 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
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system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
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system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
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system.cpu.l2cache.overall_hits::total 3 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.inst 255 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::total 308 # number of ReadReq misses
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system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses
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system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::total 389 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses
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system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
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system.cpu.l2cache.overall_misses::total 389 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13260000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::total 16016000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4212000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::total 4212000 # number of ReadExReq miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.inst 13260000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::total 20228000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 13260000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::total 20228000 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 257 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::total 311 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.inst 257 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::total 392 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.inst 257 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::total 392 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992218 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::total 0.990354 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses
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system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 255 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadReq_mshr_misses::total 308 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses
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system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10200000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12320000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3240000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3240000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10200000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 15560000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10200000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 15560000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.990354 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 82.118455 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 1253 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 9.281481 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.020048 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 1253 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 135 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 902446043 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 311 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 514 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 270 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count 784 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 16448 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8640 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size 25088 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 25088 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|