74553c7d3f
This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
415 lines
47 KiB
Text
415 lines
47 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000017 # Number of seconds simulated
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sim_ticks 16524000 # Number of ticks simulated
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final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 252355 # Simulator instruction rate (inst/s)
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host_op_rate 251860 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1611932908 # Simulator tick rate (ticks/s)
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host_mem_usage 223992 # Number of bytes of host memory used
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host_seconds 0.01 # Real time elapsed on the host
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sim_insts 2577 # Number of instructions simulated
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sim_ops 2577 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory
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system.physmem.bytes_read::total 15680 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 10432 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 10432 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 245 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 631324135 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 317598644 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 948922779 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 631324135 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 631324135 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 631324135 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 317598644 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 948922779 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 948922779 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 218 # Transaction distribution
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system.membus.trans_dist::ReadResp 218 # Transaction distribution
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system.membus.trans_dist::ReadExReq 27 # Transaction distribution
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system.membus.trans_dist::ReadExResp 27 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side 490 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count 490 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15680 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size 15680 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 15680 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 245000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 1.5 # Layer utilization (%)
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system.membus.respLayer1.occupancy 2205000 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 13.3 # Layer utilization (%)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 415 # DTB read hits
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system.cpu.dtb.read_misses 4 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 419 # DTB read accesses
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system.cpu.dtb.write_hits 294 # DTB write hits
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system.cpu.dtb.write_misses 4 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 298 # DTB write accesses
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system.cpu.dtb.data_hits 709 # DTB hits
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system.cpu.dtb.data_misses 8 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 717 # DTB accesses
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system.cpu.itb.fetch_hits 2586 # ITB hits
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system.cpu.itb.fetch_misses 11 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 2597 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 4 # Number of system calls
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system.cpu.numCycles 33048 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 2577 # Number of instructions committed
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system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
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system.cpu.num_func_calls 140 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
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system.cpu.num_int_insts 2375 # number of integer instructions
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system.cpu.num_fp_insts 6 # number of float instructions
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system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
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system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 717 # number of memory refs
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system.cpu.num_load_insts 419 # Number of load instructions
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system.cpu.num_store_insts 298 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 33048 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.tagsinuse 80.050296 # Cycle average of tags in use
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system.cpu.icache.total_refs 2423 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.039087 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 2423 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 2423 # number of overall hits
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system.cpu.icache.overall_hits::total 2423 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 163 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses
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system.cpu.icache.overall_misses::total 163 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 8965000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 8965000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 8965000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 8965000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 8965000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 2586 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 2586 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 2586 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.063032 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.063032 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8639000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 8639000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8639000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 8639000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8639000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 8639000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.tagsinuse 107.162861 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::total 0.003270 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses
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system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses
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system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::cpu.data 82 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::total 245 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses
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system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses
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system.cpu.l2cache.overall_misses::total 245 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8476000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::total 11336000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1404000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::total 1404000 # number of ReadExReq miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.inst 8476000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.data 4264000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::total 12740000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 8476000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 4264000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::total 12740000 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 163 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::total 218 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.inst 163 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.data 82 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::total 245 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.inst 163 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.data 82 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::total 245 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
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system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadReq_mshr_misses::total 218 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 245 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6520000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8720000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1080000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1080000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6520000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3280000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 9800000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6520000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3280000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 9800000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 47.437790 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.011581 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 627 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 82 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4346000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 4346000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4346000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 4346000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 948922779 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 218 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 326 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 164 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count 490 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 10432 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 5248 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size 15680 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 15680 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 244500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|