fbc1feb39a
Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
268 lines
5.2 KiB
INI
268 lines
5.2 KiB
INI
[root]
|
|
type=Root
|
|
children=system
|
|
full_system=false
|
|
time_sync_enable=false
|
|
time_sync_period=100000000000
|
|
time_sync_spin_threshold=100000000
|
|
|
|
[system]
|
|
type=System
|
|
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
|
|
boot_osflags=a
|
|
cache_line_size=64
|
|
clk_domain=system.clk_domain
|
|
init_param=0
|
|
kernel=
|
|
load_addr_mask=1099511627775
|
|
mem_mode=timing
|
|
mem_ranges=
|
|
memories=system.physmem
|
|
num_work_ids=16
|
|
readfile=
|
|
symbolfile=
|
|
work_begin_ckpt_count=0
|
|
work_begin_cpu_id_exit=-1
|
|
work_begin_exit_count=0
|
|
work_cpus_ckpt_count=0
|
|
work_end_ckpt_count=0
|
|
work_end_exit_count=0
|
|
work_item_id=-1
|
|
system_port=system.membus.slave[0]
|
|
|
|
[system.clk_domain]
|
|
type=SrcClockDomain
|
|
clock=1000
|
|
voltage_domain=system.voltage_domain
|
|
|
|
[system.cpu]
|
|
type=TimingSimpleCPU
|
|
children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
|
checker=Null
|
|
clk_domain=system.cpu_clk_domain
|
|
cpu_id=0
|
|
do_checkpoint_insts=true
|
|
do_quiesce=true
|
|
do_statistics_insts=true
|
|
dtb=system.cpu.dtb
|
|
function_trace=false
|
|
function_trace_start=0
|
|
interrupts=system.cpu.interrupts
|
|
isa=system.cpu.isa
|
|
itb=system.cpu.itb
|
|
max_insts_all_threads=0
|
|
max_insts_any_thread=0
|
|
max_loads_all_threads=0
|
|
max_loads_any_thread=0
|
|
numThreads=1
|
|
profile=0
|
|
progress_interval=0
|
|
simpoint_start_insts=
|
|
switched_out=false
|
|
system=system
|
|
tracer=system.cpu.tracer
|
|
workload=system.cpu.workload
|
|
dcache_port=system.cpu.dcache.cpu_side
|
|
icache_port=system.cpu.icache.cpu_side
|
|
|
|
[system.cpu.apic_clk_domain]
|
|
type=DerivedClockDomain
|
|
clk_divider=16
|
|
clk_domain=system.cpu_clk_domain
|
|
|
|
[system.cpu.dcache]
|
|
type=BaseCache
|
|
children=tags
|
|
addr_ranges=0:18446744073709551615
|
|
assoc=2
|
|
clk_domain=system.cpu_clk_domain
|
|
forward_snoops=true
|
|
hit_latency=2
|
|
is_top_level=true
|
|
max_miss_count=0
|
|
mshrs=4
|
|
prefetch_on_access=false
|
|
prefetcher=Null
|
|
response_latency=2
|
|
size=262144
|
|
system=system
|
|
tags=system.cpu.dcache.tags
|
|
tgts_per_mshr=20
|
|
two_queue=false
|
|
write_buffers=8
|
|
cpu_side=system.cpu.dcache_port
|
|
mem_side=system.cpu.toL2Bus.slave[1]
|
|
|
|
[system.cpu.dcache.tags]
|
|
type=LRU
|
|
assoc=2
|
|
block_size=64
|
|
clk_domain=system.cpu_clk_domain
|
|
hit_latency=2
|
|
size=262144
|
|
|
|
[system.cpu.dtb]
|
|
type=X86TLB
|
|
children=walker
|
|
size=64
|
|
walker=system.cpu.dtb.walker
|
|
|
|
[system.cpu.dtb.walker]
|
|
type=X86PagetableWalker
|
|
clk_domain=system.cpu_clk_domain
|
|
num_squash_per_cycle=4
|
|
system=system
|
|
port=system.cpu.toL2Bus.slave[3]
|
|
|
|
[system.cpu.icache]
|
|
type=BaseCache
|
|
children=tags
|
|
addr_ranges=0:18446744073709551615
|
|
assoc=2
|
|
clk_domain=system.cpu_clk_domain
|
|
forward_snoops=true
|
|
hit_latency=2
|
|
is_top_level=true
|
|
max_miss_count=0
|
|
mshrs=4
|
|
prefetch_on_access=false
|
|
prefetcher=Null
|
|
response_latency=2
|
|
size=131072
|
|
system=system
|
|
tags=system.cpu.icache.tags
|
|
tgts_per_mshr=20
|
|
two_queue=false
|
|
write_buffers=8
|
|
cpu_side=system.cpu.icache_port
|
|
mem_side=system.cpu.toL2Bus.slave[0]
|
|
|
|
[system.cpu.icache.tags]
|
|
type=LRU
|
|
assoc=2
|
|
block_size=64
|
|
clk_domain=system.cpu_clk_domain
|
|
hit_latency=2
|
|
size=131072
|
|
|
|
[system.cpu.interrupts]
|
|
type=X86LocalApic
|
|
clk_domain=system.cpu.apic_clk_domain
|
|
int_latency=1000
|
|
pio_addr=2305843009213693952
|
|
pio_latency=100000
|
|
system=system
|
|
int_master=system.membus.slave[2]
|
|
int_slave=system.membus.master[2]
|
|
pio=system.membus.master[1]
|
|
|
|
[system.cpu.isa]
|
|
type=X86ISA
|
|
|
|
[system.cpu.itb]
|
|
type=X86TLB
|
|
children=walker
|
|
size=64
|
|
walker=system.cpu.itb.walker
|
|
|
|
[system.cpu.itb.walker]
|
|
type=X86PagetableWalker
|
|
clk_domain=system.cpu_clk_domain
|
|
num_squash_per_cycle=4
|
|
system=system
|
|
port=system.cpu.toL2Bus.slave[2]
|
|
|
|
[system.cpu.l2cache]
|
|
type=BaseCache
|
|
children=tags
|
|
addr_ranges=0:18446744073709551615
|
|
assoc=8
|
|
clk_domain=system.cpu_clk_domain
|
|
forward_snoops=true
|
|
hit_latency=20
|
|
is_top_level=false
|
|
max_miss_count=0
|
|
mshrs=20
|
|
prefetch_on_access=false
|
|
prefetcher=Null
|
|
response_latency=20
|
|
size=2097152
|
|
system=system
|
|
tags=system.cpu.l2cache.tags
|
|
tgts_per_mshr=12
|
|
two_queue=false
|
|
write_buffers=8
|
|
cpu_side=system.cpu.toL2Bus.master[0]
|
|
mem_side=system.membus.slave[1]
|
|
|
|
[system.cpu.l2cache.tags]
|
|
type=LRU
|
|
assoc=8
|
|
block_size=64
|
|
clk_domain=system.cpu_clk_domain
|
|
hit_latency=20
|
|
size=2097152
|
|
|
|
[system.cpu.toL2Bus]
|
|
type=CoherentBus
|
|
clk_domain=system.cpu_clk_domain
|
|
header_cycles=1
|
|
system=system
|
|
use_default_range=false
|
|
width=32
|
|
master=system.cpu.l2cache.cpu_side
|
|
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
|
|
|
[system.cpu.tracer]
|
|
type=ExeTracer
|
|
|
|
[system.cpu.workload]
|
|
type=LiveProcess
|
|
cmd=parser 2.1.dict -batch
|
|
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
|
|
egid=100
|
|
env=
|
|
errout=cerr
|
|
euid=100
|
|
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
|
gid=100
|
|
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
|
max_stack_size=67108864
|
|
output=cout
|
|
pid=100
|
|
ppid=99
|
|
simpoint=114600000000
|
|
system=system
|
|
uid=100
|
|
|
|
[system.cpu_clk_domain]
|
|
type=SrcClockDomain
|
|
clock=500
|
|
voltage_domain=system.voltage_domain
|
|
|
|
[system.membus]
|
|
type=CoherentBus
|
|
clk_domain=system.clk_domain
|
|
header_cycles=1
|
|
system=system
|
|
use_default_range=false
|
|
width=8
|
|
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
|
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
|
|
|
[system.physmem]
|
|
type=SimpleMemory
|
|
bandwidth=73.000000
|
|
clk_domain=system.clk_domain
|
|
conf_table_reported=true
|
|
in_addr_map=true
|
|
latency=30000
|
|
latency_var=0
|
|
null=false
|
|
range=0:134217727
|
|
port=system.membus.master[0]
|
|
|
|
[system.voltage_domain]
|
|
type=VoltageDomain
|
|
voltage=1.000000
|
|
|