They are now accessed by calling readMiscReg()/setMiscReg() on the XC. Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future). arch/alpha/alpha_memory.cc: Change accesses to IPR to go through the XC. arch/alpha/ev5.cc: Change accesses for IPRs to go through the misc regs. arch/alpha/isa/decoder.isa: Change accesses to IPRs to go through the misc regs. readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect(). arch/alpha/isa/fp.isa: Change accesses to IPRs and Fpcr to go through the misc regs. arch/alpha/isa/main.isa: Add support for all misc regs being accessed through readMiscReg() and setMiscReg(). Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index. arch/alpha/isa_traits.hh: Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs. Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect. The latter are basically the original read/write IPR functions, while the former are normal reads/writes. The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs. arch/alpha/stacktrace.cc: cpu/simple/cpu.cc: dev/sinic.cc: Change accesses to the IPRs to go through the XC. arch/alpha/vtophys.cc: Change access to the IPR to go through the XC. arch/isa_parser.py: Change generation of code for control registers to use the readMiscReg and setMiscReg functions. base/remote_gdb.cc: Change accesses to the IPR to go through the XC. cpu/exec_context.hh: Use the miscRegs to access the lock addr, lock flag, and other misc registers. cpu/o3/alpha_cpu.hh: cpu/simple/cpu.hh: Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions. cpu/o3/alpha_cpu_impl.hh: Change accesses to the IPRs to go through the miscRegs. For now comment out some of the accesses to the misc regs until the proxy exec context is completed. cpu/o3/alpha_dyn_inst.hh: Change accesses to misc regs to use readMiscReg and setMiscReg. cpu/o3/alpha_dyn_inst_impl.hh: Remove old misc reg accessors. cpu/o3/cpu.cc: Comment out old misc reg accesses until the proxy exec context is completed. cpu/o3/cpu.hh: Change accesses to the misc regs. cpu/o3/regfile.hh: Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg. They are dummy functions for now until the proxy exec context is completed. kern/kernel_stats.cc: kern/system_events.cc: Have accesses to the IPRs go through the XC. kern/tru64/tru64.hh: Have accesses to the misc regs use the new access methods. --HG-- extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76
346 lines
9.1 KiB
C++
346 lines
9.1 KiB
C++
/*
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* Copyright (c) 2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <string>
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#include "arch/alpha/isa_traits.hh"
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#include "arch/alpha/stacktrace.hh"
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#include "arch/alpha/vtophys.hh"
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#include "base/bitfield.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/exec_context.hh"
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using namespace std;
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using namespace AlphaISA;
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ProcessInfo::ProcessInfo(ExecContext *_xc)
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: xc(_xc)
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{
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Addr addr = 0;
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if (!xc->system->kernelSymtab->findAddress("thread_info_size", addr))
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panic("thread info not compiled into kernel\n");
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thread_info_size = *(int32_t *)vtomem(xc, addr, sizeof(int32_t));
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if (!xc->system->kernelSymtab->findAddress("task_struct_size", addr))
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panic("thread info not compiled into kernel\n");
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task_struct_size = *(int32_t *)vtomem(xc, addr, sizeof(int32_t));
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if (!xc->system->kernelSymtab->findAddress("thread_info_task", addr))
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panic("thread info not compiled into kernel\n");
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task_off = *(int32_t *)vtomem(xc, addr, sizeof(int32_t));
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if (!xc->system->kernelSymtab->findAddress("task_struct_pid", addr))
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panic("thread info not compiled into kernel\n");
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pid_off = *(int32_t *)vtomem(xc, addr, sizeof(int32_t));
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if (!xc->system->kernelSymtab->findAddress("task_struct_comm", addr))
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panic("thread info not compiled into kernel\n");
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name_off = *(int32_t *)vtomem(xc, addr, sizeof(int32_t));
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}
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Addr
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ProcessInfo::task(Addr ksp) const
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{
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Addr base = ksp & ~0x3fff;
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if (base == ULL(0xfffffc0000000000))
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return 0;
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Addr task;
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CopyOut(xc, &task, base + task_off, sizeof(task));
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return task;
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}
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int
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ProcessInfo::pid(Addr ksp) const
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{
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Addr task = this->task(ksp);
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if (!task)
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return -1;
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uint16_t pid;
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CopyOut(xc, &pid, task + pid_off, sizeof(pid));
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return pid;
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}
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string
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ProcessInfo::name(Addr ksp) const
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{
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Addr task = this->task(ksp);
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if (!task)
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return "console";
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char comm[256];
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CopyString(xc, comm, task + name_off, sizeof(comm));
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if (!comm[0])
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return "startup";
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return comm;
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}
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StackTrace::StackTrace()
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: xc(0), stack(64)
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{
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}
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StackTrace::StackTrace(ExecContext *_xc, StaticInstPtr inst)
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: xc(0), stack(64)
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{
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trace(_xc, inst);
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}
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StackTrace::~StackTrace()
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{
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}
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void
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StackTrace::trace(ExecContext *_xc, bool is_call)
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{
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xc = _xc;
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bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
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Addr pc = xc->regs.npc;
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bool kernel = xc->system->kernelStart <= pc && pc <= xc->system->kernelEnd;
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if (usermode) {
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stack.push_back(user);
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return;
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}
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if (!kernel) {
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stack.push_back(console);
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return;
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}
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SymbolTable *symtab = xc->system->kernelSymtab;
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Addr ksp = xc->regs.intRegFile[TheISA::StackPointerReg];
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Addr bottom = ksp & ~0x3fff;
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Addr addr;
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if (is_call) {
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if (!symtab->findNearestAddr(pc, addr))
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panic("could not find address %#x", pc);
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stack.push_back(addr);
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pc = xc->regs.pc;
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}
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Addr ra;
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int size;
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while (ksp > bottom) {
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if (!symtab->findNearestAddr(pc, addr))
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panic("could not find symbol for pc=%#x", pc);
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assert(pc >= addr && "symbol botch: callpc < func");
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stack.push_back(addr);
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if (isEntry(addr))
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return;
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if (decodePrologue(ksp, pc, addr, size, ra)) {
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if (!ra)
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return;
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if (size <= 0) {
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stack.push_back(unknown);
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return;
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}
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pc = ra;
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ksp += size;
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} else {
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stack.push_back(unknown);
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return;
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}
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bool kernel = xc->system->kernelStart <= pc &&
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pc <= xc->system->kernelEnd;
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if (!kernel)
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return;
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if (stack.size() >= 1000)
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panic("unwinding too far");
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}
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panic("unwinding too far");
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}
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bool
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StackTrace::isEntry(Addr addr)
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{
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if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp12))
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return true;
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if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp7))
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return true;
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if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp11))
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return true;
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if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp21))
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return true;
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if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp9))
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return true;
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if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp2))
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return true;
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return false;
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}
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bool
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StackTrace::decodeStack(MachInst inst, int &disp)
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{
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// lda $sp, -disp($sp)
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//
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// Opcode<31:26> == 0x08
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// RA<25:21> == 30
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// RB<20:16> == 30
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// Disp<15:0>
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const MachInst mem_mask = 0xffff0000;
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const MachInst lda_pattern = 0x23de0000;
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const MachInst lda_disp_mask = 0x0000ffff;
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// subq $sp, disp, $sp
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// addq $sp, disp, $sp
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//
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// Opcode<31:26> == 0x10
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// RA<25:21> == 30
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// Lit<20:13>
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// One<12> = 1
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// Func<11:5> == 0x20 (addq)
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// Func<11:5> == 0x29 (subq)
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// RC<4:0> == 30
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const MachInst intop_mask = 0xffe01fff;
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const MachInst addq_pattern = 0x43c0141e;
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const MachInst subq_pattern = 0x43c0153e;
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const MachInst intop_disp_mask = 0x001fe000;
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const int intop_disp_shift = 13;
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if ((inst & mem_mask) == lda_pattern)
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disp = -sext<16>(inst & lda_disp_mask);
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else if ((inst & intop_mask) == addq_pattern)
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disp = -int((inst & intop_disp_mask) >> intop_disp_shift);
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else if ((inst & intop_mask) == subq_pattern)
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disp = int((inst & intop_disp_mask) >> intop_disp_shift);
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else
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return false;
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return true;
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}
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bool
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StackTrace::decodeSave(MachInst inst, int ®, int &disp)
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{
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// lda $stq, disp($sp)
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//
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// Opcode<31:26> == 0x08
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// RA<25:21> == ?
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// RB<20:16> == 30
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// Disp<15:0>
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const MachInst stq_mask = 0xfc1f0000;
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const MachInst stq_pattern = 0xb41e0000;
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const MachInst stq_disp_mask = 0x0000ffff;
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const MachInst reg_mask = 0x03e00000;
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const int reg_shift = 21;
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if ((inst & stq_mask) == stq_pattern) {
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reg = (inst & reg_mask) >> reg_shift;
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disp = sext<16>(inst & stq_disp_mask);
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} else {
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return false;
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}
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return true;
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}
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/*
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* Decode the function prologue for the function we're in, and note
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* which registers are stored where, and how large the stack frame is.
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*/
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bool
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StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func,
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int &size, Addr &ra)
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{
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size = 0;
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ra = 0;
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for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) {
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MachInst inst;
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CopyOut(xc, (uint8_t *)&inst, pc, sizeof(MachInst));
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int reg, disp;
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if (decodeStack(inst, disp)) {
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if (size) {
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// panic("decoding frame size again");
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return true;
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}
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size += disp;
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} else if (decodeSave(inst, reg, disp)) {
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if (!ra && reg == ReturnAddressReg) {
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CopyOut(xc, (uint8_t *)&ra, sp + disp, sizeof(Addr));
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if (!ra) {
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// panic("no return address value pc=%#x\n", pc);
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return false;
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}
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}
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}
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}
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return true;
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}
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#if TRACING_ON
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void
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StackTrace::dump()
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{
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StringWrap name(xc->cpu->name());
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SymbolTable *symtab = xc->system->kernelSymtab;
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DPRINTFN("------ Stack ------\n");
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string symbol;
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for (int i = 0, size = stack.size(); i < size; ++i) {
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Addr addr = stack[size - i - 1];
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if (addr == user)
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symbol = "user";
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else if (addr == console)
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symbol = "console";
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else if (addr == unknown)
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symbol = "unknown";
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else
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symtab->findSymbol(addr, symbol);
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DPRINTFN("%#x: %s\n", addr, symbol);
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}
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}
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#endif
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