570 lines
64 KiB
Text
570 lines
64 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.717366 # Number of seconds simulated
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sim_ticks 717366012000 # Number of ticks simulated
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final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 879063 # Simulator instruction rate (inst/s)
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host_op_rate 990556 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1248765490 # Simulator tick rate (ticks/s)
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host_mem_usage 313636 # Number of bytes of host memory used
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host_seconds 574.46 # Real time elapsed on the host
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sim_insts 504986853 # Number of instructions simulated
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sim_ops 569034839 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 8952256 # Number of bytes read from this memory
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system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 177280 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 177280 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 6140992 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6140992 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 2770 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 139879 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 247126 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 12479342 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 12726469 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 247126 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 247126 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 8560472 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 8560472 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 8560472 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 247126 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 12479342 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 21286941 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 21286941 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 41855 # Transaction distribution
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system.membus.trans_dist::ReadResp 41855 # Transaction distribution
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system.membus.trans_dist::Writeback 95953 # Transaction distribution
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system.membus.trans_dist::ReadExReq 100794 # Transaction distribution
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system.membus.trans_dist::ReadExResp 100794 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 15270528 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 1006226000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
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system.membus.respLayer1.occupancy 1283841000 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 548 # Number of system calls
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system.cpu.numCycles 1434732024 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 504986853 # Number of instructions committed
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system.cpu.committedOps 569034839 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
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system.cpu.num_func_calls 19311615 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls
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system.cpu.num_int_insts 470727695 # number of integer instructions
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system.cpu.num_fp_insts 16 # number of float instructions
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system.cpu.num_int_register_reads 2861859644 # number of times the integer registers were read
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system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 182890034 # number of memory refs
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system.cpu.num_load_insts 126029555 # Number of load instructions
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system.cpu.num_store_insts 56860479 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 1434732024 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.Branches 121548301 # Number of branches fetched
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system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
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system.cpu.op_class::IntAlu 387739461 67.91% 67.91% # Class of executed instruction
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system.cpu.op_class::IntMult 339219 0.06% 67.97% # Class of executed instruction
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system.cpu.op_class::IntDiv 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::FloatAdd 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::FloatCmp 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::FloatCvt 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::FloatMult 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::FloatDiv 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::FloatSqrt 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdAdd 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdAddAcc 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdAlu 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdCmp 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdCvt 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdMisc 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdMult 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdMultAcc 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdShift 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdShiftAcc 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdSqrt 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdFloatAdd 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdFloatAlu 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdFloatCmp 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdFloatCvt 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdFloatDiv 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdFloatMisc 3 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdFloatMult 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.97% # Class of executed instruction
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system.cpu.op_class::MemRead 126029555 22.07% 90.04% # Class of executed instruction
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system.cpu.op_class::MemWrite 56860479 9.96% 100.00% # Class of executed instruction
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system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::total 570968717 # Class of executed instruction
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system.cpu.icache.tags.replacements 9788 # number of replacements
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system.cpu.icache.tags.tagsinuse 982.663229 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks.
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system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks.
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system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_percent::total 0.479816 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::3 257 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::4 1403 # Occupied blocks per task id
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system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id
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system.cpu.icache.tags.tag_accesses 1033234273 # Number of tag accesses
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system.cpu.icache.tags.data_accesses 1033234273 # Number of data accesses
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system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 516599855 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 516599855 # number of overall hits
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system.cpu.icache.overall_hits::total 516599855 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
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system.cpu.icache.overall_misses::total 11521 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 266195000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 266195000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 266195000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 266195000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 266195000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 266195000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 516611376 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 516611376 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 516611376 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23105.199201 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 23105.199201 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 23105.199201 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 23105.199201 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243153000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 243153000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243153000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 243153000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243153000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 243153000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21105.199201 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21105.199201 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 109895 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 27243.192324 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 23381.854289 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.831396 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3656 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27181 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951447 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 18220084 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 18220084 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 8751 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 743573 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 752324 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1064905 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 1064905 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 255466 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 255466 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 8751 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 999039 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1007790 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 8751 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 999039 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1007790 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2770 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 39085 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 41855 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 100794 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 100794 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2770 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 139879 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 142649 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2770 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 139879 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 142649 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144122000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2033729000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 2177851000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5241304000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 5241304000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 144122000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 7275033000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 7419155000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 144122000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 7275033000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 7419155000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1064905 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 1064905 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.240431 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.049939 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.052702 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282923 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.282923 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.240431 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.122817 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.123995 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.240431 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.122817 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.123995 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52029.602888 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52033.491109 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52033.233783 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.158740 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.158740 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52029.602888 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52009.472473 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52009.863371 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52029.602888 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52009.472473 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52009.863371 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 95953 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 95953 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2770 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39085 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 41855 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100794 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 100794 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2770 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 139879 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 142649 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2770 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 139879 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 142649 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110882000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564709000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675591000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4031776000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4031776000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110882000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596485000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 5707367000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110882000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596485000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 5707367000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049939 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282923 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282923 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40029.602888 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.491109 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.233783 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 1134822 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4065.297446 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 179817786 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 157.884752 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.992504 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 363052326 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 363052326 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 176840704 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 176840704 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 176840704 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 176840704 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817433000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 11817433000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8864744000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 8864744000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 20682177000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 20682177000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 20682177000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 20682177000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 177979622 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 177979622 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 177979622 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 177979622 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.102034 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.102034 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24882.793465 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 24882.793465 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 18159.496118 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 18159.496118 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 1064905 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10252117000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10252117000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8152224000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8152224000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18404341000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 18404341000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18404341000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 18404341000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13099.102034 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13099.102034 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22882.793465 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22882.793465 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 197642506 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 141782016 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|