b00949d88b
This patch removes the assumption on having on single instance of PhysicalMemory, and enables a distributed memory where the individual memories in the system are each responsible for a single contiguous address range. All memories inherit from an AbstractMemory that encompasses the basic behaviuor of a random access memory, and provides untimed access methods. What was previously called PhysicalMemory is now SimpleMemory, and a subclass of AbstractMemory. All future types of memory controllers should inherit from AbstractMemory. To enable e.g. the atomic CPU and RubyPort to access the now distributed memory, the system has a wrapper class, called PhysicalMemory that is aware of all the memories in the system and their associated address ranges. This class thus acts as an infinitely-fast bus and performs address decoding for these "shortcut" accesses. Each memory can specify that it should not be part of the global address map (used e.g. by the functional memories by some testers). Moreover, each memory can be configured to be reported to the OS configuration table, useful for populating ATAG structures, and any potential ACPI tables. Checkpointing support currently assumes that all memories have the same size and organisation when creating and resuming from the checkpoint. A future patch will enable a more flexible re-organisation. --HG-- rename : src/mem/PhysicalMemory.py => src/mem/AbstractMemory.py rename : src/mem/PhysicalMemory.py => src/mem/SimpleMemory.py rename : src/mem/physical.cc => src/mem/abstract_mem.cc rename : src/mem/physical.hh => src/mem/abstract_mem.hh rename : src/mem/physical.cc => src/mem/simple_mem.cc rename : src/mem/physical.hh => src/mem/simple_mem.hh
289 lines
9.6 KiB
Python
289 lines
9.6 KiB
Python
# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ron Dreslinski
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# Splash2 Run Script
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#
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import os
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import optparse
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import sys
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import m5
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from m5.objects import *
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m5.util.addToPath('../common')
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# --------------------
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# Define Command Line Options
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# ====================
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parser = optparse.OptionParser()
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parser.add_option("-d", "--detailed", action="store_true")
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parser.add_option("-t", "--timing", action="store_true")
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parser.add_option("-m", "--maxtick", type="int")
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parser.add_option("-n", "--numcpus",
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help="Number of cpus in total", type="int")
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parser.add_option("-f", "--frequency",
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default = "1GHz",
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help="Frequency of each CPU")
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parser.add_option("--l1size",
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default = "32kB")
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parser.add_option("--l1latency",
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default = "1ns")
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parser.add_option("--l2size",
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default = "256kB")
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parser.add_option("--l2latency",
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default = "10ns")
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parser.add_option("--rootdir",
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help="Root directory of Splash2",
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default="/dist/splash2/codes")
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parser.add_option("-b", "--benchmark",
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help="Splash 2 benchmark to run")
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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if not options.numcpus:
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print "Specify the number of cpus with -n"
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sys.exit(1)
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# --------------------
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# Define Splash2 Benchmarks
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# ====================
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class Cholesky(LiveProcess):
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cwd = options.rootdir + '/kernels/cholesky'
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executable = options.rootdir + '/kernels/cholesky/CHOLESKY'
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cmd = ['CHOLESKY', '-p' + str(options.numcpus),
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options.rootdir + '/kernels/cholesky/inputs/tk23.O']
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class FFT(LiveProcess):
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cwd = options.rootdir + '/kernels/fft'
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executable = options.rootdir + '/kernels/fft/FFT'
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cmd = ['FFT', '-p', str(options.numcpus), '-m18']
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class LU_contig(LiveProcess):
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executable = options.rootdir + '/kernels/lu/contiguous_blocks/LU'
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cmd = ['LU', '-p', str(options.numcpus)]
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cwd = options.rootdir + '/kernels/lu/contiguous_blocks'
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class LU_noncontig(LiveProcess):
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executable = options.rootdir + '/kernels/lu/non_contiguous_blocks/LU'
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cmd = ['LU', '-p', str(options.numcpus)]
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cwd = options.rootdir + '/kernels/lu/non_contiguous_blocks'
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class Radix(LiveProcess):
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executable = options.rootdir + '/kernels/radix/RADIX'
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cmd = ['RADIX', '-n524288', '-p', str(options.numcpus)]
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cwd = options.rootdir + '/kernels/radix'
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class Barnes(LiveProcess):
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executable = options.rootdir + '/apps/barnes/BARNES'
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cmd = ['BARNES']
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input = options.rootdir + '/apps/barnes/input.p' + str(options.numcpus)
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cwd = options.rootdir + '/apps/barnes'
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class FMM(LiveProcess):
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executable = options.rootdir + '/apps/fmm/FMM'
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cmd = ['FMM']
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if str(options.numcpus) == '1':
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input = options.rootdir + '/apps/fmm/inputs/input.2048'
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else:
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input = options.rootdir + '/apps/fmm/inputs/input.2048.p' + str(options.numcpus)
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cwd = options.rootdir + '/apps/fmm'
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class Ocean_contig(LiveProcess):
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executable = options.rootdir + '/apps/ocean/contiguous_partitions/OCEAN'
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cmd = ['OCEAN', '-p', str(options.numcpus)]
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cwd = options.rootdir + '/apps/ocean/contiguous_partitions'
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class Ocean_noncontig(LiveProcess):
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executable = options.rootdir + '/apps/ocean/non_contiguous_partitions/OCEAN'
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cmd = ['OCEAN', '-p', str(options.numcpus)]
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cwd = options.rootdir + '/apps/ocean/non_contiguous_partitions'
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class Raytrace(LiveProcess):
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executable = options.rootdir + '/apps/raytrace/RAYTRACE'
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cmd = ['RAYTRACE', '-p' + str(options.numcpus),
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options.rootdir + '/apps/raytrace/inputs/teapot.env']
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cwd = options.rootdir + '/apps/raytrace'
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class Water_nsquared(LiveProcess):
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executable = options.rootdir + '/apps/water-nsquared/WATER-NSQUARED'
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cmd = ['WATER-NSQUARED']
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if options.numcpus==1:
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input = options.rootdir + '/apps/water-nsquared/input'
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else:
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input = options.rootdir + '/apps/water-nsquared/input.p' + str(options.numcpus)
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cwd = options.rootdir + '/apps/water-nsquared'
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class Water_spatial(LiveProcess):
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executable = options.rootdir + '/apps/water-spatial/WATER-SPATIAL'
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cmd = ['WATER-SPATIAL']
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if options.numcpus==1:
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input = options.rootdir + '/apps/water-spatial/input'
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else:
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input = options.rootdir + '/apps/water-spatial/input.p' + str(options.numcpus)
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cwd = options.rootdir + '/apps/water-spatial'
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# --------------------
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# Base L1 Cache Definition
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# ====================
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class L1(BaseCache):
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latency = options.l1latency
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block_size = 64
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mshrs = 12
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tgts_per_mshr = 8
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# ----------------------
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# Base L2 Cache Definition
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# ----------------------
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class L2(BaseCache):
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block_size = 64
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latency = options.l2latency
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mshrs = 92
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tgts_per_mshr = 16
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write_buffers = 8
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# ----------------------
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# Define the cpus
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# ----------------------
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busFrequency = Frequency(options.frequency)
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if options.timing:
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cpus = [TimingSimpleCPU(cpu_id = i,
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clock=options.frequency)
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for i in xrange(options.numcpus)]
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elif options.detailed:
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cpus = [DerivO3CPU(cpu_id = i,
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clock=options.frequency)
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for i in xrange(options.numcpus)]
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else:
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cpus = [AtomicSimpleCPU(cpu_id = i,
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clock=options.frequency)
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for i in xrange(options.numcpus)]
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# ----------------------
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# Create a system, and add system wide objects
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# ----------------------
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system = System(cpu = cpus, physmem = SimpleMemory(),
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membus = Bus(clock = busFrequency))
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system.toL2bus = Bus(clock = busFrequency)
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system.l2 = L2(size = options.l2size, assoc = 8)
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# ----------------------
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# Connect the L2 cache and memory together
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# ----------------------
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system.physmem.port = system.membus.master
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system.l2.cpu_side = system.toL2bus.master
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system.l2.mem_side = system.membus.slave
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system.system_port = system.membus.slave
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# ----------------------
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# Connect the L2 cache and clusters together
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# ----------------------
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for cpu in cpus:
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cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1),
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L1(size = options.l1size, assoc = 4))
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# connect cpu level-1 caches to shared level-2 cache
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cpu.connectAllPorts(system.toL2bus, system.membus)
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# ----------------------
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# Define the root
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# ----------------------
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root = Root(full_system = False, system = system)
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# --------------------
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# Pick the correct Splash2 Benchmarks
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# ====================
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if options.benchmark == 'Cholesky':
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root.workload = Cholesky()
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elif options.benchmark == 'FFT':
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root.workload = FFT()
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elif options.benchmark == 'LUContig':
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root.workload = LU_contig()
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elif options.benchmark == 'LUNoncontig':
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root.workload = LU_noncontig()
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elif options.benchmark == 'Radix':
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root.workload = Radix()
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elif options.benchmark == 'Barnes':
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root.workload = Barnes()
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elif options.benchmark == 'FMM':
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root.workload = FMM()
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elif options.benchmark == 'OceanContig':
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root.workload = Ocean_contig()
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elif options.benchmark == 'OceanNoncontig':
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root.workload = Ocean_noncontig()
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elif options.benchmark == 'Raytrace':
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root.workload = Raytrace()
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elif options.benchmark == 'WaterNSquared':
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root.workload = Water_nsquared()
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elif options.benchmark == 'WaterSpatial':
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root.workload = Water_spatial()
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else:
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print >> sys.stderr, """The --benchmark environment variable was set to something improper.
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Use Cholesky, FFT, LUContig, LUNoncontig, Radix, Barnes, FMM, OceanContig,
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OceanNoncontig, Raytrace, WaterNSquared, or WaterSpatial"""
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sys.exit(1)
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# --------------------
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# Assign the workload to the cpus
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# ====================
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for cpu in cpus:
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cpu.workload = root.workload
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# ----------------------
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# Run the simulation
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# ----------------------
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if options.timing or options.detailed:
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root.system.mem_mode = 'timing'
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# instantiate configuration
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m5.instantiate()
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# simulate until program terminates
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if options.maxtick:
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exit_event = m5.simulate(options.maxtick)
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else:
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exit_event = m5.simulate(m5.MaxTick)
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print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
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