118 lines
3.6 KiB
C++
118 lines
3.6 KiB
C++
/*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_ALPHA_ISA_HH__
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#define __ARCH_ALPHA_ISA_HH__
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#include <string>
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#include <iostream>
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#include "arch/alpha/registers.hh"
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#include "arch/alpha/types.hh"
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#include "base/types.hh"
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class BaseCPU;
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class Checkpoint;
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class EventManager;
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class ThreadContext;
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namespace AlphaISA
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{
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class ISA
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{
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public:
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typedef uint64_t InternalProcReg;
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protected:
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uint64_t fpcr; // floating point condition codes
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uint64_t uniq; // process-unique register
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bool lock_flag; // lock flag for LL/SC
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Addr lock_addr; // lock address for LL/SC
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int intr_flag;
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InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
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protected:
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InternalProcReg readIpr(int idx, ThreadContext *tc);
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void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
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public:
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MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
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MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
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void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
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ThreadID tid = 0);
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void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
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ThreadID tid = 0);
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void
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clear()
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{
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fpcr = 0;
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uniq = 0;
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lock_flag = 0;
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lock_addr = 0;
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intr_flag = 0;
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}
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void serialize(EventManager *em, std::ostream &os);
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void unserialize(EventManager *em, Checkpoint *cp,
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const std::string §ion);
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void reset(std::string core_name, ThreadID num_threads,
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unsigned num_vpes, BaseCPU *_cpu)
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{ }
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void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
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{ }
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int
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flattenIntIndex(int reg)
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{
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return reg;
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}
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int
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flattenFloatIndex(int reg)
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{
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return reg;
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}
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ISA()
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{
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clear();
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initializeIprTable();
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}
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};
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}
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#endif
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