291 lines
11 KiB
C++
291 lines
11 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_O3_DYN_INST_HH__
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#define __CPU_O3_DYN_INST_HH__
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#include "arch/isa_traits.hh"
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#include "config/the_isa.hh"
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#include "cpu/base_dyn_inst.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/o3/cpu.hh"
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#include "cpu/o3/isa_specific.hh"
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class Packet;
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/**
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* Mostly implementation & ISA specific AlphaDynInst. As with most
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* other classes in the new CPU model, it is templated on the Impl to
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* allow for passing in of all types, such as the CPU type and the ISA
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* type. The AlphaDynInst serves as the primary interface to the CPU
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* for instructions that are executing.
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*/
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template <class Impl>
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class BaseO3DynInst : public BaseDynInst<Impl>
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{
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public:
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/** Typedef for the CPU. */
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typedef typename Impl::O3CPU O3CPU;
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/** Binary machine instruction type. */
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typedef TheISA::MachInst MachInst;
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/** Extended machine instruction type. */
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typedef TheISA::ExtMachInst ExtMachInst;
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/** Logical register index type. */
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typedef TheISA::RegIndex RegIndex;
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/** Integer register index type. */
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typedef TheISA::IntReg IntReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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/** Misc register index type. */
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typedef TheISA::MiscReg MiscReg;
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enum {
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MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
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MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
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};
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public:
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/** BaseDynInst constructor given a binary instruction. */
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BaseO3DynInst(StaticInstPtr staticInst,
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TheISA::PCState pc, TheISA::PCState predPC,
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InstSeqNum seq_num, O3CPU *cpu);
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/** BaseDynInst constructor given a binary instruction. */
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BaseO3DynInst(ExtMachInst inst,
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TheISA::PCState pc, TheISA::PCState predPC,
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InstSeqNum seq_num, O3CPU *cpu);
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/** BaseDynInst constructor given a static inst pointer. */
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BaseO3DynInst(StaticInstPtr &_staticInst);
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/** Executes the instruction.*/
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Fault execute();
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/** Initiates the access. Only valid for memory operations. */
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Fault initiateAcc();
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/** Completes the access. Only valid for memory operations. */
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Fault completeAcc(PacketPtr pkt);
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private:
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/** Initializes variables. */
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void initVars();
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protected:
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/** Indexes of the destination misc. registers. They are needed to defer
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* the write accesses to the misc. registers until the commit stage, when
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* the instruction is out of its speculative state.
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*/
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int _destMiscRegIdx[MaxInstDestRegs];
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/** Values to be written to the destination misc. registers. */
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MiscReg _destMiscRegVal[MaxInstDestRegs];
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/** Number of destination misc. registers. */
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int _numDestMiscRegs;
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public:
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/** Reads a misc. register, including any side-effects the read
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* might have as defined by the architecture.
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*/
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MiscReg readMiscReg(int misc_reg)
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{
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return this->cpu->readMiscReg(misc_reg, this->threadNumber);
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}
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/** Sets a misc. register, including any side-effects the write
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* might have as defined by the architecture.
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*/
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void setMiscReg(int misc_reg, const MiscReg &val)
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{
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/** Writes to misc. registers are recorded and deferred until the
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* commit stage, when updateMiscRegs() is called.
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*/
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_destMiscRegIdx[_numDestMiscRegs] = misc_reg;
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_destMiscRegVal[_numDestMiscRegs] = val;
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_numDestMiscRegs++;
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}
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/** Reads a misc. register, including any side-effects the read
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* might have as defined by the architecture.
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*/
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TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
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{
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return this->cpu->readMiscReg(
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si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
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this->threadNumber);
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}
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/** Sets a misc. register, including any side-effects the write
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* might have as defined by the architecture.
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*/
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void setMiscRegOperand(const StaticInst *si, int idx,
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const MiscReg &val)
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{
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int misc_reg = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
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setMiscReg(misc_reg, val);
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}
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/** Called at the commit stage to update the misc. registers. */
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void updateMiscRegs()
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{
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// @todo: Pretty convoluted way to avoid squashing from happening when
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// using the TC during an instruction's execution (specifically for
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// instructions that have side-effects that use the TC). Fix this.
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// See cpu/o3/dyn_inst_impl.hh.
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bool in_syscall = this->thread->inSyscall;
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this->thread->inSyscall = true;
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for (int i = 0; i < _numDestMiscRegs; i++)
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this->cpu->setMiscReg(
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_destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
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this->thread->inSyscall = in_syscall;
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}
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void forwardOldRegs()
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{
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for (int idx = 0; idx < this->numDestRegs(); idx++) {
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PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx);
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TheISA::RegIndex original_dest_reg = this->staticInst->destRegIdx(idx);
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if (original_dest_reg < TheISA::FP_Base_DepTag)
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this->setIntRegOperand(this->staticInst.get(), idx, this->cpu->readIntReg(prev_phys_reg));
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else if (original_dest_reg < TheISA::Ctrl_Base_DepTag)
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this->setFloatRegOperandBits(this->staticInst.get(), idx, this->cpu->readFloatRegBits(prev_phys_reg));
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}
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}
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#if FULL_SYSTEM
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/** Calls hardware return from error interrupt. */
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Fault hwrei();
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/** Traps to handle specified fault. */
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void trap(Fault fault);
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bool simPalCheck(int palFunc);
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#else
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/** Calls a syscall. */
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void syscall(int64_t callnum);
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#endif
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public:
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// The register accessor methods provide the index of the
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// instruction's operand (e.g., 0 or 1), not the architectural
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// register index, to simplify the implementation of register
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// renaming. We find the architectural register index by indexing
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// into the instruction's own operand index table. Note that a
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// raw pointer to the StaticInst is provided instead of a
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// ref-counted StaticInstPtr to redice overhead. This is fine as
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// long as these methods don't copy the pointer into any long-term
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// storage (which is pretty hard to imagine they would have reason
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// to do).
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uint64_t readIntRegOperand(const StaticInst *si, int idx)
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{
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return this->cpu->readIntReg(this->_srcRegIdx[idx]);
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}
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FloatReg readFloatRegOperand(const StaticInst *si, int idx)
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{
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return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
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}
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FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
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{
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return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
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}
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/** @todo: Make results into arrays so they can handle multiple dest
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* registers.
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*/
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void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
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{
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this->cpu->setIntReg(this->_destRegIdx[idx], val);
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BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
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}
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void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
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{
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this->cpu->setFloatReg(this->_destRegIdx[idx], val);
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BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
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}
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void setFloatRegOperandBits(const StaticInst *si, int idx,
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FloatRegBits val)
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{
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this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
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BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
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}
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#if THE_ISA == MIPS_ISA
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uint64_t readRegOtherThread(int misc_reg)
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{
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panic("MIPS MT not defined for O3 CPU.\n");
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return 0;
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}
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void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
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{
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panic("MIPS MT not defined for O3 CPU.\n");
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}
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#endif
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public:
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/** Calculates EA part of a memory instruction. Currently unused,
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* though it may be useful in the future if we want to split
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* memory operations into EA calculation and memory access parts.
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*/
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Fault calcEA()
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{
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return this->staticInst->eaCompInst()->execute(this, this->traceData);
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}
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/** Does the memory access part of a memory instruction. Currently unused,
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* though it may be useful in the future if we want to split
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* memory operations into EA calculation and memory access parts.
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*/
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Fault memAccess()
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{
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return this->staticInst->memAccInst()->execute(this, this->traceData);
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}
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};
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#endif // __CPU_O3_ALPHA_DYN_INST_HH__
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