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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
Andreas Sandberg 55ed9609f1 stats: Update to match classic memory changes
2016-08-12 14:12:59 +01:00

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---------- Begin Simulation Statistics ----------
sim_seconds 51.317217 # Number of seconds simulated
sim_ticks 51317217215000 # Number of ticks simulated
final_tick 51317217215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 222365 # Simulator instruction rate (inst/s)
host_op_rate 261300 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 12534471719 # Simulator tick rate (ticks/s)
host_mem_usage 700016 # Number of bytes of host memory used
host_seconds 4094.09 # Real time elapsed on the host
sim_insts 910382802 # Number of instructions simulated
sim_ops 1069785844 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 183360 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 154432 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 3744320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 27933912 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 182144 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 147072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3576960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 29113392 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 413632 # Number of bytes read from this memory
system.physmem.bytes_read::total 65449224 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 3744320 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 3576960 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 7321280 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 83967296 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::total 83987876 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 2865 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2413 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 58505 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 436475 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 2846 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 2298 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 55890 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 454902 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6463 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1022657 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1311989 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1314562 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 3573 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 3009 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 72964 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 544338 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 3549 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 2866 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 69703 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 567322 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8060 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1275385 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 72964 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 69703 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 142667 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1636240 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1636641 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1636240 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 3573 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 3009 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 72964 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 544739 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 3549 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 2866 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 69703 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 567322 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8060 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2912027 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1022657 # Number of read requests accepted
system.physmem.writeReqs 1314562 # Number of write requests accepted
system.physmem.readBursts 1022657 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1314562 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 65407680 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 42368 # Total number of bytes read from write queue
system.physmem.bytesWritten 83988672 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 65449224 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 83987876 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 662 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2238 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 60981 # Per bank write bursts
system.physmem.perBankRdBursts::1 62566 # Per bank write bursts
system.physmem.perBankRdBursts::2 61229 # Per bank write bursts
system.physmem.perBankRdBursts::3 58916 # Per bank write bursts
system.physmem.perBankRdBursts::4 63354 # Per bank write bursts
system.physmem.perBankRdBursts::5 70912 # Per bank write bursts
system.physmem.perBankRdBursts::6 62699 # Per bank write bursts
system.physmem.perBankRdBursts::7 61112 # Per bank write bursts
system.physmem.perBankRdBursts::8 58244 # Per bank write bursts
system.physmem.perBankRdBursts::9 84348 # Per bank write bursts
system.physmem.perBankRdBursts::10 65094 # Per bank write bursts
system.physmem.perBankRdBursts::11 66290 # Per bank write bursts
system.physmem.perBankRdBursts::12 61782 # Per bank write bursts
system.physmem.perBankRdBursts::13 66140 # Per bank write bursts
system.physmem.perBankRdBursts::14 59027 # Per bank write bursts
system.physmem.perBankRdBursts::15 59301 # Per bank write bursts
system.physmem.perBankWrBursts::0 79428 # Per bank write bursts
system.physmem.perBankWrBursts::1 80879 # Per bank write bursts
system.physmem.perBankWrBursts::2 81341 # Per bank write bursts
system.physmem.perBankWrBursts::3 82396 # Per bank write bursts
system.physmem.perBankWrBursts::4 84257 # Per bank write bursts
system.physmem.perBankWrBursts::5 87543 # Per bank write bursts
system.physmem.perBankWrBursts::6 80825 # Per bank write bursts
system.physmem.perBankWrBursts::7 81935 # Per bank write bursts
system.physmem.perBankWrBursts::8 79231 # Per bank write bursts
system.physmem.perBankWrBursts::9 83962 # Per bank write bursts
system.physmem.perBankWrBursts::10 83023 # Per bank write bursts
system.physmem.perBankWrBursts::11 84619 # Per bank write bursts
system.physmem.perBankWrBursts::12 80226 # Per bank write bursts
system.physmem.perBankWrBursts::13 84960 # Per bank write bursts
system.physmem.perBankWrBursts::14 78537 # Per bank write bursts
system.physmem.perBankWrBursts::15 79161 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 117 # Number of times write queue was full causing retry
system.physmem.totGap 51317216009000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 2 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1022642 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1311989 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 563394 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 302594 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 104127 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 46335 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 752 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 511 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 662 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 460 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1269 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 340 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 384 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 210 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 200 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 145 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 131 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 122 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 106 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 99 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 84 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 795 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 741 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 737 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 732 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 726 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 727 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 723 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 722 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 720 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 725 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 723 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 722 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 720 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 716 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 723 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 21758 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 29866 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 42370 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 50746 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 67407 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 74973 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 78027 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 83029 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 86506 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 84131 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 87193 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 90592 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 82439 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 80936 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 81560 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 72513 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 71387 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 67468 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 4671 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 3626 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 2857 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 2460 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 2209 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 2161 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 2023 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1772 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1830 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1704 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1713 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1782 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1531 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1525 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1496 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 1299 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 1289 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 1434 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 1251 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 1191 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 1291 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 1069 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 1091 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 1044 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 852 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 760 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 751 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 793 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 438 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 266 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 292 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 584051 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 255.792785 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 152.875634 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 294.556382 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 254148 43.51% 43.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 146795 25.13% 68.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 55909 9.57% 78.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 27613 4.73% 82.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 21352 3.66% 86.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 11974 2.05% 88.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 10495 1.80% 90.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 7232 1.24% 91.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 48533 8.31% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 584051 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 61706 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 16.562133 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 65.554683 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 61699 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023 3 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-2559 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 61706 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 61706 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 21.267348 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.511616 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 23.799712 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-15 139 0.23% 0.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31 57235 92.75% 92.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47 1751 2.84% 95.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63 438 0.71% 96.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79 620 1.00% 97.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95 435 0.70% 98.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111 261 0.42% 98.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127 360 0.58% 99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143 146 0.24% 99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159 47 0.08% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175 57 0.09% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191 58 0.09% 99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207 16 0.03% 99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223 17 0.03% 99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239 19 0.03% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255 28 0.05% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271 17 0.03% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287 15 0.02% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303 2 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319 1 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335 1 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351 6 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367 3 0.00% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383 5 0.01% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399 4 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::400-415 4 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495 2 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::496-511 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527 3 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::608-623 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::640-655 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::672-687 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::752-767 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::768-783 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::784-799 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::832-847 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::848-863 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::864-879 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::880-895 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::896-911 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 61706 # Writes before turning the bus around for reads
system.physmem.totQLat 27544031458 # Total ticks spent queuing
system.physmem.totMemAccLat 46706437708 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 5109975000 # Total ticks spent in databus transfers
system.physmem.avgQLat 26951.24 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 45701.24 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.64 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.28 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.64 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
system.physmem.avgWrQLen 9.79 # Average write queue length when enqueuing
system.physmem.readRowHits 789656 # Number of row buffer hits during reads
system.physmem.writeRowHits 960610 # Number of row buffer hits during writes
system.physmem.readRowHitRate 77.27 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.20 # Row buffer hit rate for writes
system.physmem.avgGap 21956528.68 # Average gap between requests
system.physmem.pageHitRate 74.98 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 2223494280 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1213216125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 3913798200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 4267753920 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3351790802880 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1231075762515 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29710436097000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34304920924920 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.487622 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 49425844576094 # Time in different power states
system.physmem_0.memoryStateTime::REF 1713594480000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 177772818906 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 2191931280 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1195994250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 4057723800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 4236099120 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3351790802880 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1231757755830 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29709837865500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34305068172660 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.490491 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 49424824907095 # Time in different power states
system.physmem_1.memoryStateTime::REF 1713594480000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 178797453905 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 1408 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 2212 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 768 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 1408 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 2176 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 22 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 27 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 43 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 27 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 42 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 27 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 43 # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 134591179 # Number of BP lookups
system.cpu0.branchPred.condPredicted 90304193 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 5810526 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 90589543 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 61837798 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 68.261519 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 17370059 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 190077 # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups 5078772 # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits 2686505 # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses 2392267 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 411015 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 913460 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 913460 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17456 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 94858 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 564703 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 348757 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 2510.769676 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 14687.468261 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535 346035 99.22% 99.22% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071 1894 0.54% 99.76% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607 459 0.13% 99.89% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143 149 0.04% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679 127 0.04% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215 27 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751 61 0.02% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 348757 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 428972 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 22512.397080 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 18206.266840 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 16738.101214 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535 419694 97.84% 97.84% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071 8206 1.91% 99.75% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607 548 0.13% 99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143 418 0.10% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679 68 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215 26 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 428972 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 361724793256 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.150757 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.705483 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-3 360695140256 99.72% 99.72% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-7 568723500 0.16% 99.87% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-11 203544500 0.06% 99.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-15 117776000 0.03% 99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-19 46114500 0.01% 99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-23 23872000 0.01% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-27 26539000 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-31 36172500 0.01% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::32-35 6478000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::36-39 375000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::40-43 38000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::44-47 6500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::48-51 12500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::52-55 1000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 361724793256 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 94859 84.46% 84.46% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 17456 15.54% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 112315 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 913460 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 913460 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 112315 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 112315 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 1025775 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 106460809 # DTB read hits
system.cpu0.dtb.read_misses 623704 # DTB read misses
system.cpu0.dtb.write_hits 82932208 # DTB write hits
system.cpu0.dtb.write_misses 289756 # DTB write misses
system.cpu0.dtb.flush_tlb 1080 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 21954 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 55225 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 193 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 9182 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 56785 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 107084513 # DTB read accesses
system.cpu0.dtb.write_accesses 83221964 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 189393017 # DTB hits
system.cpu0.dtb.misses 913460 # DTB misses
system.cpu0.dtb.accesses 190306477 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 102224 # Table walker walks requested
system.cpu0.itb.walker.walksLong 102224 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2961 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69807 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 13996 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 88228 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 1371.061341 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 8977.114896 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767 87329 98.98% 98.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535 530 0.60% 99.58% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303 216 0.24% 99.83% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071 99 0.11% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839 20 0.02% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607 15 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 88228 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 86764 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 27719.480430 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23267.563993 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 18820.928470 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535 84648 97.56% 97.56% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071 1819 2.10% 99.66% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607 174 0.20% 99.86% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143 69 0.08% 99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679 30 0.03% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215 20 0.02% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 86764 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 597945449536 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.915932 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.277880 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 50325346976 8.42% 8.42% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 547568596060 91.58% 99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 46828000 0.01% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 4056500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4 391500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5 54500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::6 126500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::7 49500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 597945449536 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 69807 95.93% 95.93% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 2961 4.07% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 72768 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102224 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102224 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72768 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72768 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 174992 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 95313688 # ITB inst hits
system.cpu0.itb.inst_misses 102224 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 1080 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 21954 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 40789 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 189995 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 95415912 # ITB inst accesses
system.cpu0.itb.hits 95313688 # DTB hits
system.cpu0.itb.misses 102224 # DTB misses
system.cpu0.itb.accesses 95415912 # DTB accesses
system.cpu0.numPwrStateTransitions 16182 # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples 8091 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean 3359442146.645409 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev 64779765350.946983 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows 3624 44.79% 44.79% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10 4450 55.00% 99.79% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.80% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 3 0.04% 99.84% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 1988782283928 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total 8091 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON 24135970806492 # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 27181246408508 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 673796045 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 248201376 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 597842349 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 134591179 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 81894362 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 386081151 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 13278647 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 2497741 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 21664 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles 3050 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles 4790854 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 168722 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 2591 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 95107499 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 3628886 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 39039 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 648406203 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.078367 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.330450 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 501760932 77.38% 77.38% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 18256203 2.82% 80.20% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 18220690 2.81% 83.01% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 13435350 2.07% 85.08% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 28609960 4.41% 89.49% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 9048805 1.40% 90.89% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 9824320 1.52% 92.40% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 8413306 1.30% 93.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 40836637 6.30% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 648406203 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.199751 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.887275 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 201305382 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 321428647 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 106579942 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 13809088 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 5281102 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 19732890 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 1377081 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 652345167 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 4243358 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 5281102 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 208974593 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 22808368 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 259762289 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 112590129 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 38987372 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 636948284 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 76415 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 1870283 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 1736148 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 19269388 # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents 3866 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 608166873 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 978325960 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 751087221 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 834633 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 511551111 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 96615757 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 15505583 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 13521940 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 76964594 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 102747908 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 87125063 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 13952178 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 14707468 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 603971660 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 15594199 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 604455425 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 868037 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 82226578 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 51472860 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 368538 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 648406203 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.932217 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.660002 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 412086930 63.55% 63.55% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 99690109 15.37% 78.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 43563237 6.72% 85.65% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 31279787 4.82% 90.47% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 23126821 3.57% 94.04% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 16303260 2.51% 96.55% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 11232229 1.73% 98.28% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 6608117 1.02% 99.30% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 4515713 0.70% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 648406203 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 3047764 25.70% 25.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 24416 0.21% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 3438 0.03% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 4792960 40.42% 66.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 3990225 33.65% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 49 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 410215443 67.87% 67.87% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 1414052 0.23% 68.10% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 66288 0.01% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 164 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 69960 0.01% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 108687129 17.98% 86.10% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 84002340 13.90% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 604455425 # Type of FU issued
system.cpu0.iq.rate 0.897090 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 11858803 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.019619 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 1868979076 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 701958936 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 582265082 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 1064817 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 542988 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 473036 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 615746479 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 567700 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 4852034 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 16874429 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 20604 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 721236 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 8753871 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 4029020 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 7690355 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 5281102 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 14719425 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 6525674 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 619711534 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 1741377 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 102747908 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 87125063 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 13231258 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 247990 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 6185988 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 721236 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 2486586 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 2703924 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 5190510 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 597504652 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 106449995 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 6051495 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 145675 # number of nop insts executed
system.cpu0.iew.exec_refs 189385273 # number of memory reference insts executed
system.cpu0.iew.exec_branches 110604743 # Number of branches executed
system.cpu0.iew.exec_stores 82935278 # Number of stores executed
system.cpu0.iew.exec_rate 0.886774 # Inst execution rate
system.cpu0.iew.wb_sent 584170266 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 582738118 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 287532720 # num instructions producing a value
system.cpu0.iew.wb_consumers 500025728 # num instructions consuming a value
system.cpu0.iew.wb_rate 0.864858 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.575036 # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts 82281412 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 15225661 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 4452035 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 634456144 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.846929 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.842512 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 437517078 68.96% 68.96% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 97256113 15.33% 84.29% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 33197387 5.23% 89.52% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 15688308 2.47% 91.99% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 10938676 1.72% 93.72% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 6579950 1.04% 94.75% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 6141511 0.97% 95.72% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 3977023 0.63% 96.35% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 23160098 3.65% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 634456144 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 457096110 # Number of instructions committed
system.cpu0.commit.committedOps 537339276 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 164244670 # Number of memory references committed
system.cpu0.commit.loads 85873478 # Number of loads committed
system.cpu0.commit.membars 3759461 # Number of memory barriers committed
system.cpu0.commit.branches 102099172 # Number of branches committed
system.cpu0.commit.fp_insts 454376 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 493297626 # Number of committed integer instructions.
system.cpu0.commit.function_calls 13466186 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 371876704 69.21% 69.21% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 1107747 0.21% 69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 49726 0.01% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 60429 0.01% 69.43% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 85873478 15.98% 85.41% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 78371192 14.59% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 537339276 # Class of committed instruction
system.cpu0.commit.bw_lim_events 23160098 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 1226917419 # The number of ROB reads
system.cpu0.rob.rob_writes 1253216154 # The number of ROB writes
system.cpu0.timesIdled 4189702 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 25389842 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 54362488365 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 457096110 # Number of Instructions Simulated
system.cpu0.committedOps 537339276 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.474080 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.474080 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.678389 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.678389 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 703759932 # number of integer regfile reads
system.cpu0.int_regfile_writes 416323236 # number of integer regfile writes
system.cpu0.fp_regfile_reads 842814 # number of floating regfile reads
system.cpu0.fp_regfile_writes 524896 # number of floating regfile writes
system.cpu0.cc_regfile_reads 127590054 # number of cc regfile reads
system.cpu0.cc_regfile_writes 128777466 # number of cc regfile writes
system.cpu0.misc_regfile_reads 1210356696 # number of misc regfile reads
system.cpu0.misc_regfile_writes 15381690 # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 10779491 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.983410 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 308062266 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 10780003 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 28.577197 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 1667914500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 303.491043 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 208.492367 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.592756 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.407212 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 1359846782 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 1359846782 # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 81913095 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 81085676 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 162998771 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 68945283 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 67608016 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 136553299 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 203242 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 204927 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 408169 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 172243 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data 153828 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 326071 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1807303 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1793639 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 3600942 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2085816 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2057165 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 4142981 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 151030621 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 148847520 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 299878141 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 151233863 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 149052447 # number of overall hits
system.cpu0.dcache.overall_hits::total 300286310 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 6333331 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 6515820 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 12849151 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 6514171 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 6636089 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 13150260 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 640566 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 698533 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 1339099 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 645837 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data 595706 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 1241543 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 333547 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 322838 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 656385 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 13 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 8 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 21 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 13493339 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 13747615 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 27240954 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 14133905 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 14446148 # number of overall misses
system.cpu0.dcache.overall_misses::total 28580053 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 98901247500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 99537012000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 198438259500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 227853900939 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 237216026267 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 465069927206 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 15046942422 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 13204575493 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 28251517915 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4379004500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4078607000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 8457611500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 179500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 254000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 433500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 341802090861 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 349957613760 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 691759704621 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 341802090861 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 349957613760 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 691759704621 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 88246426 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 87601496 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 175847922 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 75459454 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 74244105 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 149703559 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 843808 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 903460 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 1747268 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 818080 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 749534 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1567614 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2140850 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2116477 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 4257327 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2085829 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2057173 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 4143002 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 164523960 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 162595135 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 327119095 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 165367768 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 163498595 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 328866363 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.071769 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.074380 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.073070 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.086327 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.089382 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.087842 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.759137 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.773175 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766396 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.789455 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.794768 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.791995 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.155801 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152536 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.154178 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000006 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000004 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082014 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.084551 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.083275 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085470 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.088356 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.086905 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15615.992201 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15276.206525 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15443.686474 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34978.188466 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35746.359982 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 35365.835140 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 23298.359218 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 22166.262373 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 22755.166688 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13128.598069 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12633.602612 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12885.138295 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13807.692308 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 31750 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20642.857143 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25331.171985 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25455.878257 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 25394.107145 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24183.132040 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24224.977742 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 24204.283478 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 50179402 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 52249 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 3620965 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 1011 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.858019 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 51.680514 # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 8246145 # number of writebacks
system.cpu0.dcache.writebacks::total 8246145 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3422225 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3613055 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 7035280 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5423611 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5531095 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 10954706 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 3582 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data 3404 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 6986 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 204425 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 198944 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 403369 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 8849418 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 9147554 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 17996972 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 8849418 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 9147554 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 17996972 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2911106 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2902765 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 5813871 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1090560 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1104994 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 2195554 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 631874 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 682564 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 1314438 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 642255 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 592302 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 1234557 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 129122 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 123894 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 253016 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 13 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 8 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 21 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 4643921 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 4600061 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 9243982 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 5275795 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 5282625 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 10558420 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17861 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 15819 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33680 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18882 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 14815 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 36743 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 30634 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67377 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45537932500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 44832999500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 90370932000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39266250291 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 40577595959 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 79843846250 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10081360000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12415038000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 22496398000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 14258396422 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 12486057493 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26744453915 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1802187500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1654747000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3456934500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 166500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 246000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 412500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99062579213 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 97896652952 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 196959232165 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 109143939213 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 110311690952 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 219455630165 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3399664500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2864633000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6264297500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3399664500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2864633000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6264297500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032988 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033136 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033062 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014452 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014883 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014666 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.748836 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.755500 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752282 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.785076 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.790227 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787539 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060313 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058538 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059431 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000006 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000004 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028226 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028292 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.028259 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031903 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.032310 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.032106 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15642.828705 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15444.929059 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15544.020843 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36005.584554 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36722.005693 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36366.150070 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15954.699829 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18188.826249 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17114.841476 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 22200.522257 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 21080.559399 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 21663.198957 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13957.245861 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13356.151226 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13662.908670 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12807.692308 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 30750 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19642.857143 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21331.667617 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21281.598864 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21306.752021 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20687.676305 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20881.984042 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20784.893020 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190340.098539 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181088.121879 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185994.581354 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92525.501456 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 93511.555788 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92973.826380 # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 16451372 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.708511 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 172021238 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 16451884 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 10.456021 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 12245439500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 287.829103 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 223.879408 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.562166 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.437264 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999431 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 287 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 206174057 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 206174057 # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 86244738 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 85776500 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 172021238 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 86244738 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 85776500 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 172021238 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 86244738 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 85776500 # number of overall hits
system.cpu0.icache.overall_hits::total 172021238 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 8850303 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 8850359 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 17700662 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 8850303 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 8850359 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 17700662 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 8850303 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 8850359 # number of overall misses
system.cpu0.icache.overall_misses::total 17700662 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 116359281374 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 116489940381 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 232849221755 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 116359281374 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 116489940381 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 232849221755 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 116359281374 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 116489940381 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 232849221755 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 95095041 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 94626859 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 189721900 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 95095041 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 94626859 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 189721900 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 95095041 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 94626859 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 189721900 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.093068 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.093529 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.093298 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.093068 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.093529 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.093298 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.093068 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.093529 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.093298 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13147.491264 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13162.171205 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13154.831257 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13147.491264 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13162.171205 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13154.831257 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13147.491264 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13162.171205 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13154.831257 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 90295 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 7581 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 11.910698 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 16451372 # number of writebacks
system.cpu0.icache.writebacks::total 16451372 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 621647 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 626857 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 1248504 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 621647 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst 626857 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 1248504 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 621647 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst 626857 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 1248504 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8228656 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8223502 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 16452158 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 8228656 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 8223502 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 16452158 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 8228656 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 8223502 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 16452158 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 12438 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 8200 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 20638 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 12438 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 8200 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 20638 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103166162413 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 103212304918 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 206378467331 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103166162413 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 103212304918 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 206378467331 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103166162413 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 103212304918 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 206378467331 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 974276500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 641521000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1615797500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 974276500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 641521000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 1615797500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086531 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.086905 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086717 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086531 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.086905 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.086717 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086531 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.086905 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.086717 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12537.425603 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12550.894366 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12544.157875 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12537.425603 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12550.894366 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12544.157875 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12537.425603 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12550.894366 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12544.157875 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 78292.349065 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 78292.349065 # average overall mshr uncacheable latency
system.cpu1.branchPred.lookups 133897441 # Number of BP lookups
system.cpu1.branchPred.condPredicted 89938186 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 5869763 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 91159166 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 61608831 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 67.583803 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 17197784 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 191914 # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups 5022071 # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits 2642299 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 2379772 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 413417 # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 900943 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 900943 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17588 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92135 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 552674 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 348269 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 2521.581019 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 15048.371457 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535 345488 99.20% 99.20% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071 1911 0.55% 99.75% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607 471 0.14% 99.89% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143 154 0.04% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679 142 0.04% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215 31 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751 66 0.02% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 348269 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 416714 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 22183.198789 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 17895.949159 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 17072.754814 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535 407840 97.87% 97.87% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 7849 1.88% 99.75% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 499 0.12% 99.87% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 336 0.08% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 108 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 63 0.02% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 13 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 416714 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 309953543704 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.014716 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.659727 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-3 308957195204 99.68% 99.68% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-7 543608000 0.18% 99.85% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-11 198540500 0.06% 99.92% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-15 120617500 0.04% 99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-19 43978000 0.01% 99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-23 24203000 0.01% 99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-27 22128500 0.01% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-31 36223000 0.01% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::32-35 6651000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::36-39 321500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::40-43 27000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::44-47 20000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::48-51 8000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::52-55 5500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::56-59 6000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::60-63 11000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 309953543704 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 92135 83.97% 83.97% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 17588 16.03% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 109723 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 900943 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 900943 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 109723 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 109723 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 1010666 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 106418453 # DTB read hits
system.cpu1.dtb.read_misses 624156 # DTB read misses
system.cpu1.dtb.write_hits 81533380 # DTB write hits
system.cpu1.dtb.write_misses 276787 # DTB write misses
system.cpu1.dtb.flush_tlb 1086 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 22079 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 55782 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 176 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 9564 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 55148 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 107042609 # DTB read accesses
system.cpu1.dtb.write_accesses 81810167 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 187951833 # DTB hits
system.cpu1.dtb.misses 900943 # DTB misses
system.cpu1.dtb.accesses 188852776 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 102336 # Table walker walks requested
system.cpu1.itb.walker.walksLong 102336 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3041 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 69360 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 14089 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 88247 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 1349.994901 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 8816.342326 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-32767 87374 99.01% 99.01% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-65535 501 0.57% 99.58% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-98303 211 0.24% 99.82% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-131071 117 0.13% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-163839 19 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-196607 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-229375 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 88247 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 86490 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 27376.708290 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 22843.157676 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 18954.672615 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535 84456 97.65% 97.65% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071 1746 2.02% 99.67% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607 174 0.20% 99.87% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143 67 0.08% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679 29 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215 9 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 86490 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 610599891424 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.922621 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.267613 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 47307697252 7.75% 7.75% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 563239770172 92.24% 99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 45620000 0.01% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3 5915500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4 874500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5 14000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 610599891424 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 69360 95.80% 95.80% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 3041 4.20% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 72401 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 102336 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 102336 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72401 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72401 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 174737 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 94847182 # ITB inst hits
system.cpu1.itb.inst_misses 102336 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 1086 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 22079 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 41108 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 191650 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 94949518 # ITB inst accesses
system.cpu1.itb.hits 94847182 # DTB hits
system.cpu1.itb.misses 102336 # DTB misses
system.cpu1.itb.accesses 94949518 # DTB accesses
system.cpu1.numPwrStateTransitions 16690 # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples 8345 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean 2811784025.136968 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev 54125884171.976646 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows 3484 41.75% 41.75% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10 4842 58.02% 99.77% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.05% 99.82% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 3 0.04% 99.89% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows 8 0.10% 100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 1988782282928 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total 8345 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON 27852879525232 # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 23464337689768 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 669110072 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 247318637 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 594168769 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 133897441 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 81448914 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 382780415 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 13369418 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 2469656 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 22020 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles 2942 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles 4831905 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 160199 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 2485 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 94635082 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 3655757 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 39111 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 644272699 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.077858 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.328781 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 498403789 77.36% 77.36% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 18180113 2.82% 80.18% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 18298329 2.84% 83.02% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 13344455 2.07% 85.09% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 28485052 4.42% 89.51% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 9005401 1.40% 90.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 9710824 1.51% 92.42% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 8365736 1.30% 93.72% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 40479000 6.28% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 644272699 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.200113 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.887999 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 200592206 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 318637226 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 105865940 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 13861849 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 5313208 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 19620033 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 1391095 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 647812132 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 4304218 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 5313208 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 208315491 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 23091878 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 256219950 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 111868936 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 39460643 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 632346200 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 89809 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 2171113 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 1552755 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 19722377 # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents 3888 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 605326116 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 973029596 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 745395954 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 835166 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 508286647 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 97039469 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 15581908 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 13599233 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 77351395 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 101957824 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 85683722 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 13730276 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 14508656 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 599162654 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 15675959 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 600368831 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 870257 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 82392045 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 51705579 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 355230 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 644272699 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.931855 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.655757 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 408550840 63.41% 63.41% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 100016688 15.52% 78.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 43398898 6.74% 85.67% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 31119922 4.83% 90.50% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 23055723 3.58% 94.08% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 16110351 2.50% 96.58% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 11122843 1.73% 98.31% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 6496596 1.01% 99.32% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 4400838 0.68% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 644272699 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 3033866 25.31% 25.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 23473 0.20% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 1799 0.02% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 4963680 41.42% 66.94% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 3962195 33.06% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 407511218 67.88% 67.88% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 1473925 0.25% 68.12% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 66979 0.01% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 186 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 16 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 1 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 14 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 58109 0.01% 68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 108674321 18.10% 86.24% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 82583972 13.76% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 600368831 # Type of FU issued
system.cpu1.iq.rate 0.897265 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 11985013 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.019963 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 1856828451 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 697391618 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 577348747 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 1037180 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 532278 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 459183 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 611800062 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 553725 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 4645881 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 16996855 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 20011 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 704534 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 8628630 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 3900409 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 8595303 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 5313208 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 14601213 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 6790244 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 614987274 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 1737370 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 101957824 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 85683722 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 13306309 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 234327 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 6472536 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 704534 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 2511910 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 2724374 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 5236284 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 593397792 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 106407717 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 6082445 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 148661 # number of nop insts executed
system.cpu1.iew.exec_refs 187941905 # number of memory reference insts executed
system.cpu1.iew.exec_branches 109851293 # Number of branches executed
system.cpu1.iew.exec_stores 81534188 # Number of stores executed
system.cpu1.iew.exec_rate 0.886846 # Inst execution rate
system.cpu1.iew.wb_sent 579236319 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 577807930 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 285288573 # num instructions producing a value
system.cpu1.iew.wb_consumers 495728954 # num instructions consuming a value
system.cpu1.iew.wb_rate 0.863547 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.575493 # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts 82442886 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 15320729 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 4497993 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 630278595 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.844780 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.835584 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 433887749 68.84% 68.84% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 97721864 15.50% 84.35% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 32952593 5.23% 89.57% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 15389192 2.44% 92.02% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 10994625 1.74% 93.76% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 6638239 1.05% 94.81% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 6092126 0.97% 95.78% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 3888165 0.62% 96.40% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 22714042 3.60% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 630278595 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 453286692 # Number of instructions committed
system.cpu1.commit.committedOps 532446568 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 162016061 # Number of memory references committed
system.cpu1.commit.loads 84960969 # Number of loads committed
system.cpu1.commit.membars 3734725 # Number of memory barriers committed
system.cpu1.commit.branches 101308962 # Number of branches committed
system.cpu1.commit.fp_insts 440790 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 488486887 # Number of committed integer instructions.
system.cpu1.commit.function_calls 13305521 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 369191199 69.34% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 1139544 0.21% 69.55% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 50295 0.01% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.56% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 49427 0.01% 69.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.57% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 84960969 15.96% 85.53% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 77055092 14.47% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 532446568 # Class of committed instruction
system.cpu1.commit.bw_lim_events 22714042 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 1218446611 # The number of ROB reads
system.cpu1.rob.rob_writes 1243796841 # The number of ROB writes
system.cpu1.timesIdled 4173884 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 24837373 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 46928670537 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 453286692 # Number of Instructions Simulated
system.cpu1.committedOps 532446568 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 1.476130 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.476130 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.677447 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.677447 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 698541221 # number of integer regfile reads
system.cpu1.int_regfile_writes 412892879 # number of integer regfile writes
system.cpu1.fp_regfile_reads 836436 # number of floating regfile reads
system.cpu1.fp_regfile_writes 478776 # number of floating regfile writes
system.cpu1.cc_regfile_reads 127759728 # number of cc regfile reads
system.cpu1.cc_regfile_writes 128888879 # number of cc regfile writes
system.cpu1.misc_regfile_reads 1201368002 # number of misc regfile reads
system.cpu1.misc_regfile_writes 15442226 # number of misc regfile writes
system.iobus.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40306 # Transaction distribution
system.iobus.trans_dist::ReadResp 40306 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230970 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230970 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 353754 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334312 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334312 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7492232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 47813000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 348500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 25706500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 40142500 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 568865504 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 147730000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115466 # number of replacements
system.iocache.tags.tagsinuse 10.425537 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115482 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 13089208816000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 5.904041 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 4.521495 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.369003 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.282593 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.651596 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1039722 # Number of tag accesses
system.iocache.tags.data_accesses 1039722 # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8821 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8858 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 115485 # number of demand (read+write) misses
system.iocache.demand_misses::total 115525 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 115485 # number of overall misses
system.iocache.overall_misses::total 115525 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5166000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1639680634 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1644846634 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 12789916870 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 12789916870 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5517000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 14429597504 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 14435114504 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5517000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 14429597504 # number of overall miss cycles
system.iocache.overall_miss_latency::total 14435114504 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8821 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8858 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 115485 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 115525 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 115485 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 115525 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 139621.621622 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 185883.758531 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 185690.520885 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119908.468368 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 119908.468368 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 137925 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124947.807109 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124952.300403 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 137925 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124947.807109 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124952.300403 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 32611 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 3377 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 9.656796 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide 8821 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8858 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide 115485 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 115525 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide 115485 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 115525 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3316000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1198630634 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1201946634 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7449853156 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 7449853156 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3517000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 8648483790 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8652000790 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3517000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 8648483790 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8652000790 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 89621.621622 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135883.758531 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 135690.520885 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69844.119440 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69844.119440 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87925 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 74888.373295 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 74892.887167 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87925 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 74888.373295 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 74892.887167 # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 1423408 # number of replacements
system.l2c.tags.tagsinuse 65419.478833 # Cycle average of tags in use
system.l2c.tags.total_refs 53105897 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1486877 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 35.716402 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 2398439000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 9244.382531 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 234.052326 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 281.998657 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4278.290194 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 23306.302204 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 255.590373 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 270.257283 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2928.362959 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 24620.242304 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.141058 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003571 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.004303 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.065282 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.355626 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003900 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.004124 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.044683 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.375675 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.998222 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 371 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 63098 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 370 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 1334 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5382 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 55988 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.005661 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.962799 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 449442160 # Number of tag accesses
system.l2c.tags.data_accesses 449442160 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker 529956 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 175456 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 523339 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 172870 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1401621 # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks 8246145 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 8246145 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 16447658 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 16447658 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 13580 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 13715 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 27295 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 13 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 19 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 799517 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 802587 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 1602104 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 8182330 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 8175499 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 16357829 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 3510444 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 3540322 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 7050766 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 354708 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 360482 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 715190 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 529956 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 175456 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 8182330 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 4309961 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 523339 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 172870 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 8175499 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 4342909 # number of demand (read+write) hits
system.l2c.demand_hits::total 26412320 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 529956 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 175456 # number of overall hits
system.l2c.overall_hits::cpu0.inst 8182330 # number of overall hits
system.l2c.overall_hits::cpu0.data 4309961 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 523339 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 172870 # number of overall hits
system.l2c.overall_hits::cpu1.inst 8175499 # number of overall hits
system.l2c.overall_hits::cpu1.data 4342909 # number of overall hits
system.l2c.overall_hits::total 26412320 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 2865 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2437 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 2846 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 2323 # number of ReadReq misses
system.l2c.ReadReq_misses::total 10471 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1976 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 2155 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 4131 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 282504 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 292518 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 575022 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 46080 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 47726 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 93806 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 154642 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 162923 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 317565 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 287547 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 231820 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 519367 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 2865 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2437 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 46080 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 437146 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 2846 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 2323 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 47726 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 455441 # number of demand (read+write) misses
system.l2c.demand_misses::total 996864 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 2865 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2437 # number of overall misses
system.l2c.overall_misses::cpu0.inst 46080 # number of overall misses
system.l2c.overall_misses::cpu0.data 437146 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 2846 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 2323 # number of overall misses
system.l2c.overall_misses::cpu1.inst 47726 # number of overall misses
system.l2c.overall_misses::cpu1.data 455441 # number of overall misses
system.l2c.overall_misses::total 996864 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 253277500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 220942000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 251257000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 208508500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 933985000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 35028000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 39186500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 74214500 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 168000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 168000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 28813882500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 29989617500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 58803500000 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 3981410000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 4106130500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 8087540500 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 14012396500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 15181111500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 29193508000 # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data 688000 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data 144500 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total 832500 # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 253277500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 220942000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 3981410000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 42826279000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 251257000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 208508500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 4106130500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 45170729000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 97018533500 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 253277500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 220942000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 3981410000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 42826279000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 251257000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 208508500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 4106130500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 45170729000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 97018533500 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 532821 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 177893 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 526185 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 175193 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1412092 # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks 8246145 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 8246145 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 16447658 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 16447658 # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 15556 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 15870 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 31426 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 13 # number of SCUpgradeReq accesses(hits+misses)
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system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2666808000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 7139023499 # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 781472499 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3176322000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 514421000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2666808000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 7139023499 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005377 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013564 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.005409 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.013117 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.007381 # mshr miss rate for ReadReq accesses
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.127025 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.135791 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.131452 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.095238 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.261089 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.267114 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.264120 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005600 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005804 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005702 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.042190 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.043992 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.043096 # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.447715 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.391388 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.420691 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.005377 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.013564 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005600 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.092084 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.005409 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.013117 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005804 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.094914 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.036367 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.005377 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.013564 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005600 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.092084 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.005409 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.013117 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005804 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.094914 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.036367 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 78403.491449 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 80889.556983 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78283.557273 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 79847.693647 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 79264.777202 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19075.151822 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19117.169374 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19097.070927 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 74000 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74000 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 91994.532955 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92522.282420 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 92263.003062 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 76403.188850 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 76035.170180 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 76215.948734 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80613.042243 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83179.567594 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 81929.786467 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20807.504530 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20901.302761 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20849.371468 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78403.491449 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80889.556983 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76403.188850 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87968.507633 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78283.557273 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79847.693647 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76035.170180 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 89180.270785 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 87325.160425 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78403.491449 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80889.556983 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76403.188850 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87968.507633 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78283.557273 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79847.693647 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76035.170180 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 89180.270785 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 87325.160425 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177835.619506 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168582.590556 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131430.161254 # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 86446.996707 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87053.861722 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 81111.441220 # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests 3173701 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 1572230 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 3254 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 54318 # Transaction distribution
system.membus.trans_dist::ReadResp 484946 # Transaction distribution
system.membus.trans_dist::WriteReq 33697 # Transaction distribution
system.membus.trans_dist::WriteResp 33697 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1311989 # Transaction distribution
system.membus.trans_dist::CleanEvict 225778 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4711 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
system.membus.trans_dist::ReadExReq 574465 # Transaction distribution
system.membus.trans_dist::ReadExResp 574465 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 430628 # Transaction distribution
system.membus.trans_dist::InvalidateReq 626011 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6864 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3984552 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4114198 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237454 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 237454 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4351652 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13728 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 142199148 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 142370922 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7237952 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7237952 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 149608874 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 3063 # Total snoops (count)
system.membus.snoopTraffic 195520 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 1723835 # Request fanout histogram
system.membus.snoop_fanout::mean 0.019089 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.136837 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 1690929 98.09% 98.09% # Request fanout histogram
system.membus.snoop_fanout::1 32906 1.91% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 1723835 # Request fanout histogram
system.membus.reqLayer0.occupancy 114103500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 5424500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 8729629317 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 5464439160 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 44651356 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 55313500 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 28081340 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 5055 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 1866 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 1866 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 2056199 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 25877432 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 33697 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 9451504 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 16451372 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2751395 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 31429 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 21 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 31450 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 2177126 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 2177126 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 16452157 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 7370941 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 1264166 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 1234557 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 49396440 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32537915 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 866839 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2547134 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 85348328 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2107113280 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1138900522 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2824688 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8472048 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 3257310538 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 2046689 # Total snoops (count)
system.toL2Bus.snoopTraffic 81942376 # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples 30811624 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.026814 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.161540 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 29985433 97.32% 97.32% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 826191 2.68% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 30811624 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 53009049492 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 1413410 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 24725297607 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 15008598618 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 514146176 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 1491177210 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 16436 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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