1445 lines
40 KiB
C++
1445 lines
40 KiB
C++
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#include <cstring>
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#include "arch/sparc/asi.hh"
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#include "arch/sparc/miscregfile.hh"
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#include "arch/sparc/tlb.hh"
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#include "base/bitfield.hh"
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#include "base/trace.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/base.hh"
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#include "mem/packet_access.hh"
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#include "mem/request.hh"
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#include "sim/system.hh"
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/* @todo remove some of the magic constants. -- ali
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* */
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namespace SparcISA {
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TLB::TLB(const Params *p)
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: SimObject(p), size(p->size), usedEntries(0), lastReplaced(0),
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cacheValid(false)
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{
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// To make this work you'll have to change the hypervisor and OS
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if (size > 64)
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fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
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tlb = new TlbEntry[size];
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std::memset(tlb, 0, sizeof(TlbEntry) * size);
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for (int x = 0; x < size; x++)
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freeList.push_back(&tlb[x]);
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c0_tsb_ps0 = 0;
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c0_tsb_ps1 = 0;
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c0_config = 0;
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cx_tsb_ps0 = 0;
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cx_tsb_ps1 = 0;
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cx_config = 0;
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sfsr = 0;
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tag_access = 0;
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}
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void
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TLB::clearUsedBits()
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{
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MapIter i;
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for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
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TlbEntry *t = i->second;
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if (!t->pte.locked()) {
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t->used = false;
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usedEntries--;
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}
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}
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}
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void
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TLB::insert(Addr va, int partition_id, int context_id, bool real,
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const PageTableEntry& PTE, int entry)
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{
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MapIter i;
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TlbEntry *new_entry = NULL;
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// TlbRange tr;
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int x;
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cacheValid = false;
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va &= ~(PTE.size()-1);
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/* tr.va = va;
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tr.size = PTE.size() - 1;
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tr.contextId = context_id;
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tr.partitionId = partition_id;
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tr.real = real;
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*/
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DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
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va, PTE.paddr(), partition_id, context_id, (int)real, entry);
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// Demap any entry that conflicts
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for (x = 0; x < size; x++) {
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if (tlb[x].range.real == real &&
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tlb[x].range.partitionId == partition_id &&
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tlb[x].range.va < va + PTE.size() - 1 &&
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tlb[x].range.va + tlb[x].range.size >= va &&
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(real || tlb[x].range.contextId == context_id ))
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{
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if (tlb[x].valid) {
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freeList.push_front(&tlb[x]);
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DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
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tlb[x].valid = false;
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if (tlb[x].used) {
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tlb[x].used = false;
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usedEntries--;
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}
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lookupTable.erase(tlb[x].range);
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}
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}
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}
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/*
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i = lookupTable.find(tr);
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if (i != lookupTable.end()) {
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i->second->valid = false;
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if (i->second->used) {
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i->second->used = false;
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usedEntries--;
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}
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freeList.push_front(i->second);
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DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
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i->second);
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lookupTable.erase(i);
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}
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*/
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if (entry != -1) {
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assert(entry < size && entry >= 0);
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new_entry = &tlb[entry];
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} else {
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if (!freeList.empty()) {
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new_entry = freeList.front();
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} else {
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x = lastReplaced;
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do {
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++x;
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if (x == size)
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x = 0;
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if (x == lastReplaced)
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goto insertAllLocked;
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} while (tlb[x].pte.locked());
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lastReplaced = x;
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new_entry = &tlb[x];
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}
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/*
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for (x = 0; x < size; x++) {
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if (!tlb[x].valid || !tlb[x].used) {
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new_entry = &tlb[x];
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break;
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}
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}*/
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}
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insertAllLocked:
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// Update the last ently if their all locked
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if (!new_entry) {
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new_entry = &tlb[size-1];
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}
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freeList.remove(new_entry);
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if (new_entry->valid && new_entry->used)
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usedEntries--;
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if (new_entry->valid)
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lookupTable.erase(new_entry->range);
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assert(PTE.valid());
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new_entry->range.va = va;
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new_entry->range.size = PTE.size() - 1;
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new_entry->range.partitionId = partition_id;
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new_entry->range.contextId = context_id;
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new_entry->range.real = real;
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new_entry->pte = PTE;
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new_entry->used = true;;
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new_entry->valid = true;
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usedEntries++;
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i = lookupTable.insert(new_entry->range, new_entry);
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assert(i != lookupTable.end());
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// If all entries have there used bit set, clear it on them all, but the
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// one we just inserted
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if (usedEntries == size) {
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clearUsedBits();
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new_entry->used = true;
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usedEntries++;
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}
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}
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TlbEntry*
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TLB::lookup(Addr va, int partition_id, bool real, int context_id, bool
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update_used)
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{
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MapIter i;
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TlbRange tr;
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TlbEntry *t;
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DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
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va, partition_id, context_id, real);
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// Assemble full address structure
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tr.va = va;
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tr.size = MachineBytes;
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tr.contextId = context_id;
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tr.partitionId = partition_id;
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tr.real = real;
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// Try to find the entry
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i = lookupTable.find(tr);
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if (i == lookupTable.end()) {
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DPRINTF(TLB, "TLB: No valid entry found\n");
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return NULL;
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}
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// Mark the entries used bit and clear other used bits in needed
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t = i->second;
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DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
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t->pte.size());
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// Update the used bits only if this is a real access (not a fake one from
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// virttophys()
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if (!t->used && update_used) {
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t->used = true;
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usedEntries++;
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if (usedEntries == size) {
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clearUsedBits();
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t->used = true;
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usedEntries++;
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}
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}
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return t;
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}
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void
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TLB::dumpAll()
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{
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MapIter i;
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for (int x = 0; x < size; x++) {
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if (tlb[x].valid) {
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DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
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x, tlb[x].range.partitionId, tlb[x].range.contextId,
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tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
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tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
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}
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}
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}
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void
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TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
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{
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TlbRange tr;
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MapIter i;
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DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
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va, partition_id, context_id, real);
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cacheValid = false;
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// Assemble full address structure
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tr.va = va;
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tr.size = MachineBytes;
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tr.contextId = context_id;
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tr.partitionId = partition_id;
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tr.real = real;
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// Demap any entry that conflicts
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i = lookupTable.find(tr);
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if (i != lookupTable.end()) {
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DPRINTF(IPR, "TLB: Demapped page\n");
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i->second->valid = false;
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if (i->second->used) {
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i->second->used = false;
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usedEntries--;
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}
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freeList.push_front(i->second);
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lookupTable.erase(i);
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}
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}
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void
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TLB::demapContext(int partition_id, int context_id)
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{
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int x;
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DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
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partition_id, context_id);
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cacheValid = false;
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for (x = 0; x < size; x++) {
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if (tlb[x].range.contextId == context_id &&
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tlb[x].range.partitionId == partition_id) {
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if (tlb[x].valid == true) {
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freeList.push_front(&tlb[x]);
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}
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tlb[x].valid = false;
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if (tlb[x].used) {
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tlb[x].used = false;
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usedEntries--;
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}
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lookupTable.erase(tlb[x].range);
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}
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}
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}
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void
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TLB::demapAll(int partition_id)
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{
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int x;
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DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
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cacheValid = false;
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for (x = 0; x < size; x++) {
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if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
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if (tlb[x].valid == true){
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freeList.push_front(&tlb[x]);
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}
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tlb[x].valid = false;
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if (tlb[x].used) {
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tlb[x].used = false;
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usedEntries--;
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}
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lookupTable.erase(tlb[x].range);
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}
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}
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}
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void
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TLB::invalidateAll()
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{
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int x;
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cacheValid = false;
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freeList.clear();
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lookupTable.clear();
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for (x = 0; x < size; x++) {
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if (tlb[x].valid == true)
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freeList.push_back(&tlb[x]);
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tlb[x].valid = false;
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tlb[x].used = false;
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}
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usedEntries = 0;
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}
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uint64_t
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TLB::TteRead(int entry) {
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if (entry >= size)
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panic("entry: %d\n", entry);
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assert(entry < size);
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if (tlb[entry].valid)
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return tlb[entry].pte();
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else
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return (uint64_t)-1ll;
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}
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uint64_t
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TLB::TagRead(int entry) {
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assert(entry < size);
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uint64_t tag;
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if (!tlb[entry].valid)
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return (uint64_t)-1ll;
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tag = tlb[entry].range.contextId;
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tag |= tlb[entry].range.va;
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tag |= (uint64_t)tlb[entry].range.partitionId << 61;
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tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
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tag |= (uint64_t)~tlb[entry].pte._size() << 56;
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return tag;
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}
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bool
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TLB::validVirtualAddress(Addr va, bool am)
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{
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if (am)
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return true;
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if (va >= StartVAddrHole && va <= EndVAddrHole)
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return false;
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return true;
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}
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void
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TLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi)
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{
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if (sfsr & 0x1)
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sfsr = 0x3;
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else
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sfsr = 1;
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if (write)
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sfsr |= 1 << 2;
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sfsr |= ct << 4;
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if (se)
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sfsr |= 1 << 6;
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sfsr |= ft << 7;
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sfsr |= asi << 16;
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}
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void
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TLB::writeTagAccess(Addr va, int context)
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{
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DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
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va, context, mbits(va, 63,13) | mbits(context,12,0));
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tag_access = mbits(va, 63,13) | mbits(context,12,0);
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}
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void
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ITB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi)
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{
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DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n",
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(int)write, ct, ft, asi);
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TLB::writeSfsr(write, ct, se, ft, asi);
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}
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void
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DTB::writeSfsr(Addr a, bool write, ContextType ct,
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bool se, FaultTypes ft, int asi)
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{
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DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
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a, (int)write, ct, ft, asi);
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TLB::writeSfsr(write, ct, se, ft, asi);
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sfar = a;
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}
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Fault
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ITB::translate(RequestPtr &req, ThreadContext *tc)
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{
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uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
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Addr vaddr = req->getVaddr();
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TlbEntry *e;
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assert(req->getAsi() == ASI_IMPLICIT);
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DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
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vaddr, req->getSize());
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// Be fast if we can!
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if (cacheValid && cacheState == tlbdata) {
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if (cacheEntry) {
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if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
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cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
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req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) |
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vaddr & cacheEntry->pte.size()-1 );
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return NoFault;
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}
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} else {
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req->setPaddr(vaddr & PAddrImplMask);
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return NoFault;
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}
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}
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bool hpriv = bits(tlbdata,0,0);
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bool red = bits(tlbdata,1,1);
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bool priv = bits(tlbdata,2,2);
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bool addr_mask = bits(tlbdata,3,3);
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bool lsu_im = bits(tlbdata,4,4);
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int part_id = bits(tlbdata,15,8);
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int tl = bits(tlbdata,18,16);
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int pri_context = bits(tlbdata,47,32);
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int context;
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ContextType ct;
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int asi;
|
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bool real = false;
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DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
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priv, hpriv, red, lsu_im, part_id);
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if (tl > 0) {
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asi = ASI_N;
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ct = Nucleus;
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context = 0;
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} else {
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asi = ASI_P;
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ct = Primary;
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context = pri_context;
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}
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if ( hpriv || red ) {
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cacheValid = true;
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cacheState = tlbdata;
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cacheEntry = NULL;
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req->setPaddr(vaddr & PAddrImplMask);
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return NoFault;
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}
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|
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// If the access is unaligned trap
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if (vaddr & 0x3) {
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writeSfsr(false, ct, false, OtherFault, asi);
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return new MemAddressNotAligned;
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}
|
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|
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if (addr_mask)
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vaddr = vaddr & VAddrAMask;
|
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|
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if (!validVirtualAddress(vaddr, addr_mask)) {
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writeSfsr(false, ct, false, VaOutOfRange, asi);
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return new InstructionAccessException;
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}
|
|
|
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if (!lsu_im) {
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e = lookup(vaddr, part_id, true);
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real = true;
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context = 0;
|
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} else {
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e = lookup(vaddr, part_id, false, context);
|
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}
|
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|
|
if (e == NULL || !e->valid) {
|
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writeTagAccess(vaddr, context);
|
|
if (real)
|
|
return new InstructionRealTranslationMiss;
|
|
else
|
|
#if FULL_SYSTEM
|
|
return new FastInstructionAccessMMUMiss;
|
|
#else
|
|
return new FastInstructionAccessMMUMiss(req->getVaddr());
|
|
#endif
|
|
}
|
|
|
|
// were not priviledged accesing priv page
|
|
if (!priv && e->pte.priv()) {
|
|
writeTagAccess(vaddr, context);
|
|
writeSfsr(false, ct, false, PrivViolation, asi);
|
|
return new InstructionAccessException;
|
|
}
|
|
|
|
// cache translation date for next translation
|
|
cacheValid = true;
|
|
cacheState = tlbdata;
|
|
cacheEntry = e;
|
|
|
|
req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
|
|
vaddr & e->pte.size()-1 );
|
|
DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
|
|
return NoFault;
|
|
}
|
|
|
|
|
|
|
|
Fault
|
|
DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
|
|
{
|
|
/* @todo this could really use some profiling and fixing to make it faster! */
|
|
uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
|
|
Addr vaddr = req->getVaddr();
|
|
Addr size = req->getSize();
|
|
ASI asi;
|
|
asi = (ASI)req->getAsi();
|
|
bool implicit = false;
|
|
bool hpriv = bits(tlbdata,0,0);
|
|
bool unaligned = (vaddr & size-1);
|
|
|
|
DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
|
|
vaddr, size, asi);
|
|
|
|
if (lookupTable.size() != 64 - freeList.size())
|
|
panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
|
|
freeList.size());
|
|
if (asi == ASI_IMPLICIT)
|
|
implicit = true;
|
|
|
|
// Only use the fast path here if there doesn't need to be an unaligned
|
|
// trap later
|
|
if (!unaligned) {
|
|
if (hpriv && implicit) {
|
|
req->setPaddr(vaddr & PAddrImplMask);
|
|
return NoFault;
|
|
}
|
|
|
|
// Be fast if we can!
|
|
if (cacheValid && cacheState == tlbdata) {
|
|
|
|
|
|
|
|
if (cacheEntry[0]) {
|
|
TlbEntry *ce = cacheEntry[0];
|
|
Addr ce_va = ce->range.va;
|
|
if (cacheAsi[0] == asi &&
|
|
ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
|
|
(!write || ce->pte.writable())) {
|
|
req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
|
|
if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
|
|
req->setFlags(req->getFlags() | UNCACHEABLE);
|
|
DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
|
|
return NoFault;
|
|
} // if matched
|
|
} // if cache entry valid
|
|
if (cacheEntry[1]) {
|
|
TlbEntry *ce = cacheEntry[1];
|
|
Addr ce_va = ce->range.va;
|
|
if (cacheAsi[1] == asi &&
|
|
ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
|
|
(!write || ce->pte.writable())) {
|
|
req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
|
|
if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
|
|
req->setFlags(req->getFlags() | UNCACHEABLE);
|
|
DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
|
|
return NoFault;
|
|
} // if matched
|
|
} // if cache entry valid
|
|
}
|
|
}
|
|
|
|
bool red = bits(tlbdata,1,1);
|
|
bool priv = bits(tlbdata,2,2);
|
|
bool addr_mask = bits(tlbdata,3,3);
|
|
bool lsu_dm = bits(tlbdata,5,5);
|
|
|
|
int part_id = bits(tlbdata,15,8);
|
|
int tl = bits(tlbdata,18,16);
|
|
int pri_context = bits(tlbdata,47,32);
|
|
int sec_context = bits(tlbdata,63,48);
|
|
|
|
bool real = false;
|
|
ContextType ct = Primary;
|
|
int context = 0;
|
|
|
|
TlbEntry *e;
|
|
|
|
DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
|
|
priv, hpriv, red, lsu_dm, part_id);
|
|
|
|
if (implicit) {
|
|
if (tl > 0) {
|
|
asi = ASI_N;
|
|
ct = Nucleus;
|
|
context = 0;
|
|
} else {
|
|
asi = ASI_P;
|
|
ct = Primary;
|
|
context = pri_context;
|
|
}
|
|
} else {
|
|
// We need to check for priv level/asi priv
|
|
if (!priv && !hpriv && !AsiIsUnPriv(asi)) {
|
|
// It appears that context should be Nucleus in these cases?
|
|
writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
|
|
return new PrivilegedAction;
|
|
}
|
|
|
|
if (!hpriv && AsiIsHPriv(asi)) {
|
|
writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
|
|
return new DataAccessException;
|
|
}
|
|
|
|
if (AsiIsPrimary(asi)) {
|
|
context = pri_context;
|
|
ct = Primary;
|
|
} else if (AsiIsSecondary(asi)) {
|
|
context = sec_context;
|
|
ct = Secondary;
|
|
} else if (AsiIsNucleus(asi)) {
|
|
ct = Nucleus;
|
|
context = 0;
|
|
} else { // ????
|
|
ct = Primary;
|
|
context = pri_context;
|
|
}
|
|
}
|
|
|
|
if (!implicit && asi != ASI_P && asi != ASI_S) {
|
|
if (AsiIsLittle(asi))
|
|
panic("Little Endian ASIs not supported\n");
|
|
|
|
//XXX It's unclear from looking at the documentation how a no fault
|
|
//load differs from a regular one, other than what happens concerning
|
|
//nfo and e bits in the TTE
|
|
// if (AsiIsNoFault(asi))
|
|
// panic("No Fault ASIs not supported\n");
|
|
|
|
if (AsiIsPartialStore(asi))
|
|
panic("Partial Store ASIs not supported\n");
|
|
|
|
if (AsiIsCmt(asi))
|
|
panic("Cmt ASI registers not implmented\n");
|
|
|
|
if (AsiIsInterrupt(asi))
|
|
goto handleIntRegAccess;
|
|
if (AsiIsMmu(asi))
|
|
goto handleMmuRegAccess;
|
|
if (AsiIsScratchPad(asi))
|
|
goto handleScratchRegAccess;
|
|
if (AsiIsQueue(asi))
|
|
goto handleQueueRegAccess;
|
|
if (AsiIsSparcError(asi))
|
|
goto handleSparcErrorRegAccess;
|
|
|
|
if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) &&
|
|
!AsiIsTwin(asi) && !AsiIsBlock(asi) && !AsiIsNoFault(asi))
|
|
panic("Accessing ASI %#X. Should we?\n", asi);
|
|
}
|
|
|
|
// If the asi is unaligned trap
|
|
if (unaligned) {
|
|
writeSfsr(vaddr, false, ct, false, OtherFault, asi);
|
|
return new MemAddressNotAligned;
|
|
}
|
|
|
|
if (addr_mask)
|
|
vaddr = vaddr & VAddrAMask;
|
|
|
|
if (!validVirtualAddress(vaddr, addr_mask)) {
|
|
writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi);
|
|
return new DataAccessException;
|
|
}
|
|
|
|
|
|
if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) {
|
|
real = true;
|
|
context = 0;
|
|
};
|
|
|
|
if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
|
|
req->setPaddr(vaddr & PAddrImplMask);
|
|
return NoFault;
|
|
}
|
|
|
|
e = lookup(vaddr, part_id, real, context);
|
|
|
|
if (e == NULL || !e->valid) {
|
|
writeTagAccess(vaddr, context);
|
|
DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
|
|
if (real)
|
|
return new DataRealTranslationMiss;
|
|
else
|
|
#if FULL_SYSTEM
|
|
return new FastDataAccessMMUMiss;
|
|
#else
|
|
return new FastDataAccessMMUMiss(req->getVaddr());
|
|
#endif
|
|
|
|
}
|
|
|
|
if (!priv && e->pte.priv()) {
|
|
writeTagAccess(vaddr, context);
|
|
writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
|
|
return new DataAccessException;
|
|
}
|
|
|
|
if (write && !e->pte.writable()) {
|
|
writeTagAccess(vaddr, context);
|
|
writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
|
|
return new FastDataAccessProtection;
|
|
}
|
|
|
|
if (e->pte.nofault() && !AsiIsNoFault(asi)) {
|
|
writeTagAccess(vaddr, context);
|
|
writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
|
|
return new DataAccessException;
|
|
}
|
|
|
|
if (e->pte.sideffect() && AsiIsNoFault(asi)) {
|
|
writeTagAccess(vaddr, context);
|
|
writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
|
|
return new DataAccessException;
|
|
}
|
|
|
|
|
|
if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
|
|
req->setFlags(req->getFlags() | UNCACHEABLE);
|
|
|
|
// cache translation date for next translation
|
|
cacheState = tlbdata;
|
|
if (!cacheValid) {
|
|
cacheEntry[1] = NULL;
|
|
cacheEntry[0] = NULL;
|
|
}
|
|
|
|
if (cacheEntry[0] != e && cacheEntry[1] != e) {
|
|
cacheEntry[1] = cacheEntry[0];
|
|
cacheEntry[0] = e;
|
|
cacheAsi[1] = cacheAsi[0];
|
|
cacheAsi[0] = asi;
|
|
if (implicit)
|
|
cacheAsi[0] = (ASI)0;
|
|
}
|
|
cacheValid = true;
|
|
req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
|
|
vaddr & e->pte.size()-1);
|
|
DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
|
|
return NoFault;
|
|
|
|
/** Normal flow ends here. */
|
|
handleIntRegAccess:
|
|
if (!hpriv) {
|
|
writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
|
|
if (priv)
|
|
return new DataAccessException;
|
|
else
|
|
return new PrivilegedAction;
|
|
}
|
|
|
|
if (asi == ASI_SWVR_UDB_INTR_W && !write ||
|
|
asi == ASI_SWVR_UDB_INTR_R && write) {
|
|
writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
|
|
return new DataAccessException;
|
|
}
|
|
|
|
goto regAccessOk;
|
|
|
|
|
|
handleScratchRegAccess:
|
|
if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
|
|
writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
|
|
return new DataAccessException;
|
|
}
|
|
goto regAccessOk;
|
|
|
|
handleQueueRegAccess:
|
|
if (!priv && !hpriv) {
|
|
writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
|
|
return new PrivilegedAction;
|
|
}
|
|
if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
|
|
writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
|
|
return new DataAccessException;
|
|
}
|
|
goto regAccessOk;
|
|
|
|
handleSparcErrorRegAccess:
|
|
if (!hpriv) {
|
|
writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
|
|
if (priv)
|
|
return new DataAccessException;
|
|
else
|
|
return new PrivilegedAction;
|
|
}
|
|
goto regAccessOk;
|
|
|
|
|
|
regAccessOk:
|
|
handleMmuRegAccess:
|
|
DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
|
|
req->setMmapedIpr(true);
|
|
req->setPaddr(req->getVaddr());
|
|
return NoFault;
|
|
};
|
|
|
|
#if FULL_SYSTEM
|
|
|
|
Tick
|
|
DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
|
|
{
|
|
Addr va = pkt->getAddr();
|
|
ASI asi = (ASI)pkt->req->getAsi();
|
|
uint64_t temp;
|
|
|
|
DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
|
|
(uint32_t)pkt->req->getAsi(), pkt->getAddr());
|
|
|
|
ITB * itb = tc->getITBPtr();
|
|
|
|
switch (asi) {
|
|
case ASI_LSU_CONTROL_REG:
|
|
assert(va == 0);
|
|
pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
|
|
break;
|
|
case ASI_MMU:
|
|
switch (va) {
|
|
case 0x8:
|
|
pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
|
|
break;
|
|
case 0x10:
|
|
pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
|
|
break;
|
|
default:
|
|
goto doMmuReadError;
|
|
}
|
|
break;
|
|
case ASI_QUEUE:
|
|
pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
|
|
(va >> 4) - 0x3c));
|
|
break;
|
|
case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
|
|
assert(va == 0);
|
|
pkt->set(c0_tsb_ps0);
|
|
break;
|
|
case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
|
|
assert(va == 0);
|
|
pkt->set(c0_tsb_ps1);
|
|
break;
|
|
case ASI_DMMU_CTXT_ZERO_CONFIG:
|
|
assert(va == 0);
|
|
pkt->set(c0_config);
|
|
break;
|
|
case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
|
|
assert(va == 0);
|
|
pkt->set(itb->c0_tsb_ps0);
|
|
break;
|
|
case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
|
|
assert(va == 0);
|
|
pkt->set(itb->c0_tsb_ps1);
|
|
break;
|
|
case ASI_IMMU_CTXT_ZERO_CONFIG:
|
|
assert(va == 0);
|
|
pkt->set(itb->c0_config);
|
|
break;
|
|
case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
|
|
assert(va == 0);
|
|
pkt->set(cx_tsb_ps0);
|
|
break;
|
|
case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
|
|
assert(va == 0);
|
|
pkt->set(cx_tsb_ps1);
|
|
break;
|
|
case ASI_DMMU_CTXT_NONZERO_CONFIG:
|
|
assert(va == 0);
|
|
pkt->set(cx_config);
|
|
break;
|
|
case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
|
|
assert(va == 0);
|
|
pkt->set(itb->cx_tsb_ps0);
|
|
break;
|
|
case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
|
|
assert(va == 0);
|
|
pkt->set(itb->cx_tsb_ps1);
|
|
break;
|
|
case ASI_IMMU_CTXT_NONZERO_CONFIG:
|
|
assert(va == 0);
|
|
pkt->set(itb->cx_config);
|
|
break;
|
|
case ASI_SPARC_ERROR_STATUS_REG:
|
|
pkt->set((uint64_t)0);
|
|
break;
|
|
case ASI_HYP_SCRATCHPAD:
|
|
case ASI_SCRATCHPAD:
|
|
pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
|
|
break;
|
|
case ASI_IMMU:
|
|
switch (va) {
|
|
case 0x0:
|
|
temp = itb->tag_access;
|
|
pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
|
|
break;
|
|
case 0x18:
|
|
pkt->set(itb->sfsr);
|
|
break;
|
|
case 0x30:
|
|
pkt->set(itb->tag_access);
|
|
break;
|
|
default:
|
|
goto doMmuReadError;
|
|
}
|
|
break;
|
|
case ASI_DMMU:
|
|
switch (va) {
|
|
case 0x0:
|
|
temp = tag_access;
|
|
pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
|
|
break;
|
|
case 0x18:
|
|
pkt->set(sfsr);
|
|
break;
|
|
case 0x20:
|
|
pkt->set(sfar);
|
|
break;
|
|
case 0x30:
|
|
pkt->set(tag_access);
|
|
break;
|
|
case 0x80:
|
|
pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID));
|
|
break;
|
|
default:
|
|
goto doMmuReadError;
|
|
}
|
|
break;
|
|
case ASI_DMMU_TSB_PS0_PTR_REG:
|
|
pkt->set(MakeTsbPtr(Ps0,
|
|
tag_access,
|
|
c0_tsb_ps0,
|
|
c0_config,
|
|
cx_tsb_ps0,
|
|
cx_config));
|
|
break;
|
|
case ASI_DMMU_TSB_PS1_PTR_REG:
|
|
pkt->set(MakeTsbPtr(Ps1,
|
|
tag_access,
|
|
c0_tsb_ps1,
|
|
c0_config,
|
|
cx_tsb_ps1,
|
|
cx_config));
|
|
break;
|
|
case ASI_IMMU_TSB_PS0_PTR_REG:
|
|
pkt->set(MakeTsbPtr(Ps0,
|
|
itb->tag_access,
|
|
itb->c0_tsb_ps0,
|
|
itb->c0_config,
|
|
itb->cx_tsb_ps0,
|
|
itb->cx_config));
|
|
break;
|
|
case ASI_IMMU_TSB_PS1_PTR_REG:
|
|
pkt->set(MakeTsbPtr(Ps1,
|
|
itb->tag_access,
|
|
itb->c0_tsb_ps1,
|
|
itb->c0_config,
|
|
itb->cx_tsb_ps1,
|
|
itb->cx_config));
|
|
break;
|
|
case ASI_SWVR_INTR_RECEIVE:
|
|
pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
|
|
break;
|
|
case ASI_SWVR_UDB_INTR_R:
|
|
temp = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
|
|
tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp);
|
|
pkt->set(temp);
|
|
break;
|
|
default:
|
|
doMmuReadError:
|
|
panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
|
|
(uint32_t)asi, va);
|
|
}
|
|
pkt->makeAtomicResponse();
|
|
return tc->getCpuPtr()->ticks(1);
|
|
}
|
|
|
|
Tick
|
|
DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
|
|
{
|
|
uint64_t data = gtoh(pkt->get<uint64_t>());
|
|
Addr va = pkt->getAddr();
|
|
ASI asi = (ASI)pkt->req->getAsi();
|
|
|
|
Addr ta_insert;
|
|
Addr va_insert;
|
|
Addr ct_insert;
|
|
int part_insert;
|
|
int entry_insert = -1;
|
|
bool real_insert;
|
|
bool ignore;
|
|
int part_id;
|
|
int ctx_id;
|
|
PageTableEntry pte;
|
|
|
|
DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
|
|
(uint32_t)asi, va, data);
|
|
|
|
ITB * itb = tc->getITBPtr();
|
|
|
|
switch (asi) {
|
|
case ASI_LSU_CONTROL_REG:
|
|
assert(va == 0);
|
|
tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);
|
|
break;
|
|
case ASI_MMU:
|
|
switch (va) {
|
|
case 0x8:
|
|
tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data);
|
|
break;
|
|
case 0x10:
|
|
tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data);
|
|
break;
|
|
default:
|
|
goto doMmuWriteError;
|
|
}
|
|
break;
|
|
case ASI_QUEUE:
|
|
assert(mbits(data,13,6) == data);
|
|
tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
|
|
(va >> 4) - 0x3c, data);
|
|
break;
|
|
case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
|
|
assert(va == 0);
|
|
c0_tsb_ps0 = data;
|
|
break;
|
|
case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
|
|
assert(va == 0);
|
|
c0_tsb_ps1 = data;
|
|
break;
|
|
case ASI_DMMU_CTXT_ZERO_CONFIG:
|
|
assert(va == 0);
|
|
c0_config = data;
|
|
break;
|
|
case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
|
|
assert(va == 0);
|
|
itb->c0_tsb_ps0 = data;
|
|
break;
|
|
case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
|
|
assert(va == 0);
|
|
itb->c0_tsb_ps1 = data;
|
|
break;
|
|
case ASI_IMMU_CTXT_ZERO_CONFIG:
|
|
assert(va == 0);
|
|
itb->c0_config = data;
|
|
break;
|
|
case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
|
|
assert(va == 0);
|
|
cx_tsb_ps0 = data;
|
|
break;
|
|
case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
|
|
assert(va == 0);
|
|
cx_tsb_ps1 = data;
|
|
break;
|
|
case ASI_DMMU_CTXT_NONZERO_CONFIG:
|
|
assert(va == 0);
|
|
cx_config = data;
|
|
break;
|
|
case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
|
|
assert(va == 0);
|
|
itb->cx_tsb_ps0 = data;
|
|
break;
|
|
case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
|
|
assert(va == 0);
|
|
itb->cx_tsb_ps1 = data;
|
|
break;
|
|
case ASI_IMMU_CTXT_NONZERO_CONFIG:
|
|
assert(va == 0);
|
|
itb->cx_config = data;
|
|
break;
|
|
case ASI_SPARC_ERROR_EN_REG:
|
|
case ASI_SPARC_ERROR_STATUS_REG:
|
|
warn("Ignoring write to SPARC ERROR regsiter\n");
|
|
break;
|
|
case ASI_HYP_SCRATCHPAD:
|
|
case ASI_SCRATCHPAD:
|
|
tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
|
|
break;
|
|
case ASI_IMMU:
|
|
switch (va) {
|
|
case 0x18:
|
|
itb->sfsr = data;
|
|
break;
|
|
case 0x30:
|
|
sext<59>(bits(data, 59,0));
|
|
itb->tag_access = data;
|
|
break;
|
|
default:
|
|
goto doMmuWriteError;
|
|
}
|
|
break;
|
|
case ASI_ITLB_DATA_ACCESS_REG:
|
|
entry_insert = bits(va, 8,3);
|
|
case ASI_ITLB_DATA_IN_REG:
|
|
assert(entry_insert != -1 || mbits(va,10,9) == va);
|
|
ta_insert = itb->tag_access;
|
|
va_insert = mbits(ta_insert, 63,13);
|
|
ct_insert = mbits(ta_insert, 12,0);
|
|
part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
|
|
real_insert = bits(va, 9,9);
|
|
pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
|
|
PageTableEntry::sun4u);
|
|
tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
|
|
pte, entry_insert);
|
|
break;
|
|
case ASI_DTLB_DATA_ACCESS_REG:
|
|
entry_insert = bits(va, 8,3);
|
|
case ASI_DTLB_DATA_IN_REG:
|
|
assert(entry_insert != -1 || mbits(va,10,9) == va);
|
|
ta_insert = tag_access;
|
|
va_insert = mbits(ta_insert, 63,13);
|
|
ct_insert = mbits(ta_insert, 12,0);
|
|
part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
|
|
real_insert = bits(va, 9,9);
|
|
pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
|
|
PageTableEntry::sun4u);
|
|
insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
|
|
break;
|
|
case ASI_IMMU_DEMAP:
|
|
ignore = false;
|
|
ctx_id = -1;
|
|
part_id = tc->readMiscReg(MISCREG_MMU_PART_ID);
|
|
switch (bits(va,5,4)) {
|
|
case 0:
|
|
ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
|
|
break;
|
|
case 1:
|
|
ignore = true;
|
|
break;
|
|
case 3:
|
|
ctx_id = 0;
|
|
break;
|
|
default:
|
|
ignore = true;
|
|
}
|
|
|
|
switch(bits(va,7,6)) {
|
|
case 0: // demap page
|
|
if (!ignore)
|
|
tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
|
|
bits(va,9,9), ctx_id);
|
|
break;
|
|
case 1: //demap context
|
|
if (!ignore)
|
|
tc->getITBPtr()->demapContext(part_id, ctx_id);
|
|
break;
|
|
case 2:
|
|
tc->getITBPtr()->demapAll(part_id);
|
|
break;
|
|
default:
|
|
panic("Invalid type for IMMU demap\n");
|
|
}
|
|
break;
|
|
case ASI_DMMU:
|
|
switch (va) {
|
|
case 0x18:
|
|
sfsr = data;
|
|
break;
|
|
case 0x30:
|
|
sext<59>(bits(data, 59,0));
|
|
tag_access = data;
|
|
break;
|
|
case 0x80:
|
|
tc->setMiscReg(MISCREG_MMU_PART_ID, data);
|
|
break;
|
|
default:
|
|
goto doMmuWriteError;
|
|
}
|
|
break;
|
|
case ASI_DMMU_DEMAP:
|
|
ignore = false;
|
|
ctx_id = -1;
|
|
part_id = tc->readMiscReg(MISCREG_MMU_PART_ID);
|
|
switch (bits(va,5,4)) {
|
|
case 0:
|
|
ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
|
|
break;
|
|
case 1:
|
|
ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT);
|
|
break;
|
|
case 3:
|
|
ctx_id = 0;
|
|
break;
|
|
default:
|
|
ignore = true;
|
|
}
|
|
|
|
switch(bits(va,7,6)) {
|
|
case 0: // demap page
|
|
if (!ignore)
|
|
demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
|
|
break;
|
|
case 1: //demap context
|
|
if (!ignore)
|
|
demapContext(part_id, ctx_id);
|
|
break;
|
|
case 2:
|
|
demapAll(part_id);
|
|
break;
|
|
default:
|
|
panic("Invalid type for IMMU demap\n");
|
|
}
|
|
break;
|
|
case ASI_SWVR_INTR_RECEIVE:
|
|
int msb;
|
|
// clear all the interrupts that aren't set in the write
|
|
while(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data) {
|
|
msb = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data);
|
|
tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb);
|
|
}
|
|
break;
|
|
case ASI_SWVR_UDB_INTR_W:
|
|
tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
|
|
post_interrupt(bits(data,5,0),0);
|
|
break;
|
|
default:
|
|
doMmuWriteError:
|
|
panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
|
|
(uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
|
|
}
|
|
pkt->makeAtomicResponse();
|
|
return tc->getCpuPtr()->ticks(1);
|
|
}
|
|
|
|
#endif
|
|
|
|
void
|
|
DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
|
|
{
|
|
uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
|
|
ITB * itb = tc->getITBPtr();
|
|
ptrs[0] = MakeTsbPtr(Ps0, tag_access,
|
|
c0_tsb_ps0,
|
|
c0_config,
|
|
cx_tsb_ps0,
|
|
cx_config);
|
|
ptrs[1] = MakeTsbPtr(Ps1, tag_access,
|
|
c0_tsb_ps1,
|
|
c0_config,
|
|
cx_tsb_ps1,
|
|
cx_config);
|
|
ptrs[2] = MakeTsbPtr(Ps0, tag_access,
|
|
itb->c0_tsb_ps0,
|
|
itb->c0_config,
|
|
itb->cx_tsb_ps0,
|
|
itb->cx_config);
|
|
ptrs[3] = MakeTsbPtr(Ps1, tag_access,
|
|
itb->c0_tsb_ps1,
|
|
itb->c0_config,
|
|
itb->cx_tsb_ps1,
|
|
itb->cx_config);
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
uint64_t
|
|
DTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
|
|
uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config)
|
|
{
|
|
uint64_t tsb;
|
|
uint64_t config;
|
|
|
|
if (bits(tag_access, 12,0) == 0) {
|
|
tsb = c0_tsb;
|
|
config = c0_config;
|
|
} else {
|
|
tsb = cX_tsb;
|
|
config = cX_config;
|
|
}
|
|
|
|
uint64_t ptr = mbits(tsb,63,13);
|
|
bool split = bits(tsb,12,12);
|
|
int tsb_size = bits(tsb,3,0);
|
|
int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8);
|
|
|
|
if (ps == Ps1 && split)
|
|
ptr |= ULL(1) << (13 + tsb_size);
|
|
ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4);
|
|
|
|
return ptr;
|
|
}
|
|
|
|
|
|
void
|
|
TLB::serialize(std::ostream &os)
|
|
{
|
|
SERIALIZE_SCALAR(size);
|
|
SERIALIZE_SCALAR(usedEntries);
|
|
SERIALIZE_SCALAR(lastReplaced);
|
|
|
|
// convert the pointer based free list into an index based one
|
|
int *free_list = (int*)malloc(sizeof(int) * size);
|
|
int cntr = 0;
|
|
std::list<TlbEntry*>::iterator i;
|
|
i = freeList.begin();
|
|
while (i != freeList.end()) {
|
|
free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry);
|
|
i++;
|
|
}
|
|
SERIALIZE_SCALAR(cntr);
|
|
SERIALIZE_ARRAY(free_list, cntr);
|
|
|
|
for (int x = 0; x < size; x++) {
|
|
nameOut(os, csprintf("%s.PTE%d", name(), x));
|
|
tlb[x].serialize(os);
|
|
}
|
|
|
|
SERIALIZE_SCALAR(c0_tsb_ps0);
|
|
SERIALIZE_SCALAR(c0_tsb_ps1);
|
|
SERIALIZE_SCALAR(c0_config);
|
|
SERIALIZE_SCALAR(cx_tsb_ps0);
|
|
SERIALIZE_SCALAR(cx_tsb_ps1);
|
|
SERIALIZE_SCALAR(cx_config);
|
|
SERIALIZE_SCALAR(sfsr);
|
|
SERIALIZE_SCALAR(tag_access);
|
|
}
|
|
|
|
void
|
|
TLB::unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
int oldSize;
|
|
|
|
paramIn(cp, section, "size", oldSize);
|
|
if (oldSize != size)
|
|
panic("Don't support unserializing different sized TLBs\n");
|
|
UNSERIALIZE_SCALAR(usedEntries);
|
|
UNSERIALIZE_SCALAR(lastReplaced);
|
|
|
|
int cntr;
|
|
UNSERIALIZE_SCALAR(cntr);
|
|
|
|
int *free_list = (int*)malloc(sizeof(int) * cntr);
|
|
freeList.clear();
|
|
UNSERIALIZE_ARRAY(free_list, cntr);
|
|
for (int x = 0; x < cntr; x++)
|
|
freeList.push_back(&tlb[free_list[x]]);
|
|
|
|
lookupTable.clear();
|
|
for (int x = 0; x < size; x++) {
|
|
tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x));
|
|
if (tlb[x].valid)
|
|
lookupTable.insert(tlb[x].range, &tlb[x]);
|
|
|
|
}
|
|
|
|
UNSERIALIZE_SCALAR(c0_tsb_ps0);
|
|
UNSERIALIZE_SCALAR(c0_tsb_ps1);
|
|
UNSERIALIZE_SCALAR(c0_config);
|
|
UNSERIALIZE_SCALAR(cx_tsb_ps0);
|
|
UNSERIALIZE_SCALAR(cx_tsb_ps1);
|
|
UNSERIALIZE_SCALAR(cx_config);
|
|
UNSERIALIZE_SCALAR(sfsr);
|
|
UNSERIALIZE_SCALAR(tag_access);
|
|
}
|
|
|
|
void
|
|
DTB::serialize(std::ostream &os)
|
|
{
|
|
TLB::serialize(os);
|
|
SERIALIZE_SCALAR(sfar);
|
|
}
|
|
|
|
void
|
|
DTB::unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
TLB::unserialize(cp, section);
|
|
UNSERIALIZE_SCALAR(sfar);
|
|
}
|
|
|
|
/* end namespace SparcISA */ }
|
|
|
|
SparcISA::ITB *
|
|
SparcITBParams::create()
|
|
{
|
|
return new SparcISA::ITB(this);
|
|
}
|
|
|
|
SparcISA::DTB *
|
|
SparcDTBParams::create()
|
|
{
|
|
return new SparcISA::DTB(this);
|
|
}
|