74e8abd37e
cpu/cpu_exec_context.cc:
Be sure to switch over the kernel stats so things don't get messed up. This may lead to weird stats files for sampling runs (detailed stats should be correct, regardless of which kernel stats this is defined on).
cpu/o3/cpu.cc:
Updates for switching out. Also include a bunch of debug info if needed.
cpu/o3/fetch_impl.hh:
Switch out properly.
cpu/o3/inst_queue.hh:
cpu/o3/inst_queue_impl.hh:
Comment out unused stats (they made the stats file huge).
cpu/o3/lsq_unit.hh:
cpu/o3/lsq_unit_impl.hh:
Add in new stat.
cpu/o3/rename.hh:
Fix up for switching out.
cpu/o3/rename_impl.hh:
Fix up for switching out. Be sure to mark any Misc regs as ready if their renamed inst got squashed from being switched out.
cpu/ozone/cpu_impl.hh:
cpu/simple/cpu.cc:
Switch out fixup.
sim/eventq.hh:
Make CPU switching more immediate.
Also comment out the assertion, as it doesn't apply if we're putting it on an inst-based queue.
--HG--
extra : convert_revision : f40ed40604738993f061e0c628810ff37a920562
661 lines
22 KiB
C++
661 lines
22 KiB
C++
/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_LSQ_UNIT_HH__
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#define __CPU_O3_LSQ_UNIT_HH__
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#include <algorithm>
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#include <map>
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#include <queue>
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#include "arch/faults.hh"
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#include "config/full_system.hh"
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#include "base/hashmap.hh"
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#include "cpu/inst_seq.hh"
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#include "mem/mem_interface.hh"
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//#include "mem/page_table.hh"
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//#include "sim/debug.hh"
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//#include "sim/sim_object.hh"
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/**
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* Class that implements the actual LQ and SQ for each specific
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* thread. Both are circular queues; load entries are freed upon
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* committing, while store entries are freed once they writeback. The
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* LSQUnit tracks if there are memory ordering violations, and also
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* detects partial load to store forwarding cases (a store only has
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* part of a load's data) that requires the load to wait until the
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* store writes back. In the former case it holds onto the instruction
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* until the dependence unit looks at it, and in the latter it stalls
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* the LSQ until the store writes back. At that point the load is
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* replayed.
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*/
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template <class Impl>
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class LSQUnit {
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protected:
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typedef TheISA::IntReg IntReg;
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public:
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typedef typename Impl::Params Params;
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typedef typename Impl::FullCPU FullCPU;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::CPUPol::IEW IEW;
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typedef typename Impl::CPUPol::IssueStruct IssueStruct;
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private:
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class StoreCompletionEvent : public Event {
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public:
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/** Constructs a store completion event. */
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StoreCompletionEvent(int store_idx, Event *wb_event, LSQUnit *lsq_ptr);
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/** Processes the store completion event. */
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void process();
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/** Returns the description of this event. */
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const char *description();
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/** The writeback event for the store. Needed for store
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* conditionals.
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*/
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Event *wbEvent;
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private:
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/** The store index of the store being written back. */
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int storeIdx;
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private:
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/** The pointer to the LSQ unit that issued the store. */
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LSQUnit<Impl> *lsqPtr;
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};
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public:
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/** Constructs an LSQ unit. init() must be called prior to use. */
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LSQUnit();
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/** Initializes the LSQ unit with the specified number of entries. */
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void init(Params *params, unsigned maxLQEntries,
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unsigned maxSQEntries, unsigned id);
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/** Returns the name of the LSQ unit. */
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std::string name() const;
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/** Registers statistics. */
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void regStats();
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/** Sets the CPU pointer. */
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void setCPU(FullCPU *cpu_ptr)
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{ cpu = cpu_ptr; }
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/** Sets the IEW stage pointer. */
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void setIEW(IEW *iew_ptr)
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{ iewStage = iew_ptr; }
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/** Sets the page table pointer. */
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// void setPageTable(PageTable *pt_ptr);
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/** Switches out LSQ unit. */
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void switchOut();
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/** Takes over from another CPU's thread. */
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void takeOverFrom();
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/** Returns if the LSQ is switched out. */
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bool isSwitchedOut() { return switchedOut; }
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/** Ticks the LSQ unit, which in this case only resets the number of
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* used cache ports.
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* @todo: Move the number of used ports up to the LSQ level so it can
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* be shared by all LSQ units.
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*/
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void tick() { usedPorts = 0; }
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/** Inserts an instruction. */
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void insert(DynInstPtr &inst);
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/** Inserts a load instruction. */
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void insertLoad(DynInstPtr &load_inst);
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/** Inserts a store instruction. */
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void insertStore(DynInstPtr &store_inst);
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/** Executes a load instruction. */
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Fault executeLoad(DynInstPtr &inst);
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Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
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/** Executes a store instruction. */
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Fault executeStore(DynInstPtr &inst);
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/** Commits the head load. */
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void commitLoad();
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/** Commits loads older than a specific sequence number. */
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void commitLoads(InstSeqNum &youngest_inst);
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/** Commits stores older than a specific sequence number. */
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void commitStores(InstSeqNum &youngest_inst);
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/** Writes back stores. */
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void writebackStores();
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/** Clears all the entries in the LQ. */
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void clearLQ();
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/** Clears all the entries in the SQ. */
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void clearSQ();
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/** Resizes the LQ to a given size. */
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void resizeLQ(unsigned size);
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/** Resizes the SQ to a given size. */
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void resizeSQ(unsigned size);
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/** Squashes all instructions younger than a specific sequence number. */
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void squash(const InstSeqNum &squashed_num);
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/** Returns if there is a memory ordering violation. Value is reset upon
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* call to getMemDepViolator().
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*/
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bool violation() { return memDepViolator; }
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/** Returns the memory ordering violator. */
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DynInstPtr getMemDepViolator();
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/** Returns if a load became blocked due to the memory system. */
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bool loadBlocked()
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{ return isLoadBlocked; }
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/** Clears the signal that a load became blocked. */
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void clearLoadBlocked()
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{ isLoadBlocked = false; }
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/** Returns if the blocked load was handled. */
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bool isLoadBlockedHandled()
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{ return loadBlockedHandled; }
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/** Records the blocked load as being handled. */
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void setLoadBlockedHandled()
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{ loadBlockedHandled = true; }
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/** Returns the number of free entries (min of free LQ and SQ entries). */
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unsigned numFreeEntries();
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/** Returns the number of loads ready to execute. */
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int numLoadsReady();
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/** Returns the number of loads in the LQ. */
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int numLoads() { return loads; }
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/** Returns the number of stores in the SQ. */
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int numStores() { return stores; }
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/** Returns if either the LQ or SQ is full. */
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bool isFull() { return lqFull() || sqFull(); }
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/** Returns if the LQ is full. */
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bool lqFull() { return loads >= (LQEntries - 1); }
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/** Returns if the SQ is full. */
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bool sqFull() { return stores >= (SQEntries - 1); }
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/** Returns the number of instructions in the LSQ. */
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unsigned getCount() { return loads + stores; }
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/** Returns if there are any stores to writeback. */
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bool hasStoresToWB() { return storesToWB; }
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/** Returns the number of stores to writeback. */
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int numStoresToWB() { return storesToWB; }
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/** Returns if the LSQ unit will writeback on this cycle. */
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bool willWB() { return storeQueue[storeWBIdx].canWB &&
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!storeQueue[storeWBIdx].completed &&
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!dcacheInterface->isBlocked(); }
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private:
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/** Completes the store at the specified index. */
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void completeStore(int store_idx);
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/** Increments the given store index (circular queue). */
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inline void incrStIdx(int &store_idx);
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/** Decrements the given store index (circular queue). */
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inline void decrStIdx(int &store_idx);
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/** Increments the given load index (circular queue). */
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inline void incrLdIdx(int &load_idx);
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/** Decrements the given load index (circular queue). */
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inline void decrLdIdx(int &load_idx);
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public:
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/** Debugging function to dump instructions in the LSQ. */
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void dumpInsts();
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private:
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/** Pointer to the CPU. */
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FullCPU *cpu;
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/** Pointer to the IEW stage. */
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IEW *iewStage;
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/** Pointer to the D-cache. */
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MemInterface *dcacheInterface;
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/** Pointer to the page table. */
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// PageTable *pTable;
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public:
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struct SQEntry {
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/** Constructs an empty store queue entry. */
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SQEntry()
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: inst(NULL), req(NULL), size(0), data(0),
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canWB(0), committed(0), completed(0)
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{ }
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/** Constructs a store queue entry for a given instruction. */
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SQEntry(DynInstPtr &_inst)
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: inst(_inst), req(NULL), size(0), data(0),
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canWB(0), committed(0), completed(0)
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{ }
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/** The store instruction. */
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DynInstPtr inst;
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/** The memory request for the store. */
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MemReqPtr req;
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/** The size of the store. */
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int size;
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/** The store data. */
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IntReg data;
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/** Whether or not the store can writeback. */
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bool canWB;
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/** Whether or not the store is committed. */
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bool committed;
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/** Whether or not the store is completed. */
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bool completed;
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};
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private:
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/** The LSQUnit thread id. */
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unsigned lsqID;
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/** The store queue. */
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std::vector<SQEntry> storeQueue;
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/** The load queue. */
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std::vector<DynInstPtr> loadQueue;
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/** The number of LQ entries, plus a sentinel entry (circular queue).
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* @todo: Consider having var that records the true number of LQ entries.
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*/
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unsigned LQEntries;
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/** The number of SQ entries, plus a sentinel entry (circular queue).
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* @todo: Consider having var that records the true number of SQ entries.
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*/
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unsigned SQEntries;
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/** The number of load instructions in the LQ. */
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int loads;
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/** The number of store instructions in the SQ. */
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int stores;
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/** The number of store instructions in the SQ waiting to writeback. */
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int storesToWB;
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/** The index of the head instruction in the LQ. */
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int loadHead;
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/** The index of the tail instruction in the LQ. */
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int loadTail;
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/** The index of the head instruction in the SQ. */
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int storeHead;
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/** The index of the first instruction that may be ready to be
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* written back, and has not yet been written back.
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*/
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int storeWBIdx;
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/** The index of the tail instruction in the SQ. */
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int storeTail;
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/// @todo Consider moving to a more advanced model with write vs read ports
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/** The number of cache ports available each cycle. */
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int cachePorts;
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/** The number of used cache ports in this cycle. */
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int usedPorts;
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/** Is the LSQ switched out. */
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bool switchedOut;
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//list<InstSeqNum> mshrSeqNums;
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/** Wire to read information from the issue stage time queue. */
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typename TimeBuffer<IssueStruct>::wire fromIssue;
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/** Whether or not the LSQ is stalled. */
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bool stalled;
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/** The store that causes the stall due to partial store to load
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* forwarding.
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*/
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InstSeqNum stallingStoreIsn;
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/** The index of the above store. */
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int stallingLoadIdx;
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/** Whether or not a load is blocked due to the memory system. */
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bool isLoadBlocked;
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/** Has the blocked load been handled. */
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bool loadBlockedHandled;
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/** The sequence number of the blocked load. */
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InstSeqNum blockedLoadSeqNum;
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/** The oldest load that caused a memory ordering violation. */
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DynInstPtr memDepViolator;
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// Will also need how many read/write ports the Dcache has. Or keep track
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// of that in stage that is one level up, and only call executeLoad/Store
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// the appropriate number of times.
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/** Total number of loads forwaded from LSQ stores. */
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Stats::Scalar<> lsqForwLoads;
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/** Total number of loads ignored due to invalid addresses. */
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Stats::Scalar<> invAddrLoads;
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/** Total number of squashed loads. */
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Stats::Scalar<> lsqSquashedLoads;
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/** Total number of responses from the memory system that are
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* ignored due to the instruction already being squashed. */
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Stats::Scalar<> lsqIgnoredResponses;
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/** Tota number of memory ordering violations. */
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Stats::Scalar<> lsqMemOrderViolation;
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/** Total number of squashed stores. */
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Stats::Scalar<> lsqSquashedStores;
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/** Total number of software prefetches ignored due to invalid addresses. */
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Stats::Scalar<> invAddrSwpfs;
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/** Ready loads blocked due to partial store-forwarding. */
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Stats::Scalar<> lsqBlockedLoads;
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/** Number of loads that were rescheduled. */
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Stats::Scalar<> lsqRescheduledLoads;
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/** Number of times the LSQ is blocked due to the cache. */
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Stats::Scalar<> lsqCacheBlocked;
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public:
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/** Executes the load at the given index. */
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template <class T>
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Fault read(MemReqPtr &req, T &data, int load_idx);
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/** Executes the store at the given index. */
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template <class T>
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Fault write(MemReqPtr &req, T &data, int store_idx);
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/** Returns the index of the head load instruction. */
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int getLoadHead() { return loadHead; }
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/** Returns the sequence number of the head load instruction. */
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InstSeqNum getLoadHeadSeqNum()
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{
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if (loadQueue[loadHead]) {
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return loadQueue[loadHead]->seqNum;
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} else {
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return 0;
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}
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}
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/** Returns the index of the head store instruction. */
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int getStoreHead() { return storeHead; }
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/** Returns the sequence number of the head store instruction. */
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InstSeqNum getStoreHeadSeqNum()
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{
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if (storeQueue[storeHead].inst) {
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return storeQueue[storeHead].inst->seqNum;
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} else {
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return 0;
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}
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}
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/** Returns whether or not the LSQ unit is stalled. */
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bool isStalled() { return stalled; }
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};
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template <class Impl>
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template <class T>
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Fault
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LSQUnit<Impl>::read(MemReqPtr &req, T &data, int load_idx)
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{
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assert(loadQueue[load_idx]);
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assert(!loadQueue[load_idx]->isExecuted());
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// Make sure this isn't an uncacheable access
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// A bit of a hackish way to get uncached accesses to work only if they're
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// at the head of the LSQ and are ready to commit (at the head of the ROB
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// too).
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if (req->flags & UNCACHEABLE &&
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(load_idx != loadHead || !loadQueue[load_idx]->isAtCommit())) {
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iewStage->rescheduleMemInst(loadQueue[load_idx]);
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++lsqRescheduledLoads;
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return TheISA::genMachineCheckFault();
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}
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// Check the SQ for any previous stores that might lead to forwarding
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int store_idx = loadQueue[load_idx]->sqIdx;
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int store_size = 0;
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DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
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"storeHead: %i addr: %#x\n",
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load_idx, store_idx, storeHead, req->paddr);
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#if 0
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if (req->flags & LOCKED) {
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cpu->lockAddr = req->paddr;
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cpu->lockFlag = true;
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}
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#endif
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req->cmd = Read;
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assert(!req->completionEvent);
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req->completionEvent = NULL;
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req->time = curTick;
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while (store_idx != -1) {
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// End once we've reached the top of the LSQ
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if (store_idx == storeWBIdx) {
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break;
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}
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// Move the index to one younger
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if (--store_idx < 0)
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store_idx += SQEntries;
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assert(storeQueue[store_idx].inst);
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store_size = storeQueue[store_idx].size;
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if (store_size == 0)
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continue;
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// Check if the store data is within the lower and upper bounds of
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// addresses that the request needs.
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bool store_has_lower_limit =
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req->vaddr >= storeQueue[store_idx].inst->effAddr;
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bool store_has_upper_limit =
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(req->vaddr + req->size) <= (storeQueue[store_idx].inst->effAddr +
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store_size);
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bool lower_load_has_store_part =
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req->vaddr < (storeQueue[store_idx].inst->effAddr +
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store_size);
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bool upper_load_has_store_part =
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(req->vaddr + req->size) > storeQueue[store_idx].inst->effAddr;
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// If the store's data has all of the data needed, we can forward.
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if (store_has_lower_limit && store_has_upper_limit) {
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// Get shift amount for offset into the store's data.
|
|
int shift_amt = req->vaddr & (store_size - 1);
|
|
// @todo: Magic number, assumes byte addressing
|
|
shift_amt = shift_amt << 3;
|
|
|
|
// Cast this to type T?
|
|
data = storeQueue[store_idx].data >> shift_amt;
|
|
|
|
assert(!req->data);
|
|
req->data = new uint8_t[64];
|
|
|
|
memcpy(req->data, &data, req->size);
|
|
|
|
DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
|
|
"addr %#x, data %#x\n",
|
|
store_idx, req->vaddr, *(req->data));
|
|
|
|
typename IEW::LdWritebackEvent *wb =
|
|
new typename IEW::LdWritebackEvent(loadQueue[load_idx],
|
|
iewStage);
|
|
|
|
// We'll say this has a 1 cycle load-store forwarding latency
|
|
// for now.
|
|
// @todo: Need to make this a parameter.
|
|
wb->schedule(curTick);
|
|
|
|
// Should keep track of stat for forwarded data
|
|
return NoFault;
|
|
} else if ((store_has_lower_limit && lower_load_has_store_part) ||
|
|
(store_has_upper_limit && upper_load_has_store_part) ||
|
|
(lower_load_has_store_part && upper_load_has_store_part)) {
|
|
// This is the partial store-load forwarding case where a store
|
|
// has only part of the load's data.
|
|
|
|
// If it's already been written back, then don't worry about
|
|
// stalling on it.
|
|
if (storeQueue[store_idx].completed) {
|
|
continue;
|
|
}
|
|
|
|
// Must stall load and force it to retry, so long as it's the oldest
|
|
// load that needs to do so.
|
|
if (!stalled ||
|
|
(stalled &&
|
|
loadQueue[load_idx]->seqNum <
|
|
loadQueue[stallingLoadIdx]->seqNum)) {
|
|
stalled = true;
|
|
stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
|
|
stallingLoadIdx = load_idx;
|
|
}
|
|
|
|
// Tell IQ/mem dep unit that this instruction will need to be
|
|
// rescheduled eventually
|
|
iewStage->rescheduleMemInst(loadQueue[load_idx]);
|
|
iewStage->decrWb(loadQueue[load_idx]->seqNum);
|
|
++lsqRescheduledLoads;
|
|
|
|
// Do not generate a writeback event as this instruction is not
|
|
// complete.
|
|
DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
|
|
"Store idx %i to load addr %#x\n",
|
|
store_idx, req->vaddr);
|
|
|
|
++lsqBlockedLoads;
|
|
return NoFault;
|
|
}
|
|
}
|
|
|
|
// If there's no forwarding case, then go access memory
|
|
DynInstPtr inst = loadQueue[load_idx];
|
|
|
|
DPRINTF(LSQUnit, "Doing functional access for inst [sn:%lli] PC %#x\n",
|
|
loadQueue[load_idx]->seqNum, loadQueue[load_idx]->readPC());
|
|
|
|
assert(!req->data);
|
|
req->data = new uint8_t[64];
|
|
Fault fault = cpu->read(req, data);
|
|
memcpy(req->data, &data, sizeof(T));
|
|
|
|
++usedPorts;
|
|
|
|
// if we have a cache, do cache access too
|
|
if (fault == NoFault && dcacheInterface) {
|
|
if (dcacheInterface->isBlocked()) {
|
|
++lsqCacheBlocked;
|
|
|
|
iewStage->decrWb(inst->seqNum);
|
|
|
|
// There's an older load that's already going to squash.
|
|
if (isLoadBlocked && blockedLoadSeqNum < inst->seqNum)
|
|
return NoFault;
|
|
|
|
// Record that the load was blocked due to memory. This
|
|
// load will squash all instructions after it, be
|
|
// refetched, and re-executed.
|
|
isLoadBlocked = true;
|
|
loadBlockedHandled = false;
|
|
blockedLoadSeqNum = inst->seqNum;
|
|
// No fault occurred, even though the interface is blocked.
|
|
return NoFault;
|
|
}
|
|
|
|
DPRINTF(LSQUnit, "Doing timing access for inst PC %#x\n",
|
|
loadQueue[load_idx]->readPC());
|
|
|
|
assert(!req->completionEvent);
|
|
req->completionEvent =
|
|
new typename IEW::LdWritebackEvent(loadQueue[load_idx], iewStage);
|
|
MemAccessResult result = dcacheInterface->access(req);
|
|
|
|
assert(dcacheInterface->doEvents());
|
|
|
|
if (result != MA_HIT) {
|
|
DPRINTF(LSQUnit, "LSQUnit: D-cache miss!\n");
|
|
DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
|
|
inst->seqNum);
|
|
} else {
|
|
DPRINTF(LSQUnit, "LSQUnit: D-cache hit!\n");
|
|
DPRINTF(Activity, "Activity: ld accessing mem hit [sn:%lli]\n",
|
|
inst->seqNum);
|
|
}
|
|
}
|
|
|
|
return fault;
|
|
}
|
|
|
|
template <class Impl>
|
|
template <class T>
|
|
Fault
|
|
LSQUnit<Impl>::write(MemReqPtr &req, T &data, int store_idx)
|
|
{
|
|
assert(storeQueue[store_idx].inst);
|
|
|
|
DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x"
|
|
" | storeHead:%i [sn:%i]\n",
|
|
store_idx, req->paddr, data, storeHead,
|
|
storeQueue[store_idx].inst->seqNum);
|
|
|
|
storeQueue[store_idx].req = req;
|
|
storeQueue[store_idx].size = sizeof(T);
|
|
storeQueue[store_idx].data = data;
|
|
|
|
// This function only writes the data to the store queue, so no fault
|
|
// can happen here.
|
|
return NoFault;
|
|
}
|
|
|
|
#endif // __CPU_O3_LSQ_UNIT_HH__
|