cpu/cpu_exec_context.cc:
Be sure to switch over the kernel stats so things don't get messed up. This may lead to weird stats files for sampling runs (detailed stats should be correct, regardless of which kernel stats this is defined on).
cpu/o3/cpu.cc:
Updates for switching out. Also include a bunch of debug info if needed.
cpu/o3/fetch_impl.hh:
Switch out properly.
cpu/o3/inst_queue.hh:
cpu/o3/inst_queue_impl.hh:
Comment out unused stats (they made the stats file huge).
cpu/o3/lsq_unit.hh:
cpu/o3/lsq_unit_impl.hh:
Add in new stat.
cpu/o3/rename.hh:
Fix up for switching out.
cpu/o3/rename_impl.hh:
Fix up for switching out. Be sure to mark any Misc regs as ready if their renamed inst got squashed from being switched out.
cpu/ozone/cpu_impl.hh:
cpu/simple/cpu.cc:
Switch out fixup.
sim/eventq.hh:
Make CPU switching more immediate.
Also comment out the assertion, as it doesn't apply if we're putting it on an inst-based queue.
--HG--
extra : convert_revision : f40ed40604738993f061e0c628810ff37a920562
cpu/activity.cc:
cpu/activity.hh:
cpu/o3/alpha_cpu.hh:
Updates to include comments.
cpu/base_dyn_inst.cc:
Remove call to thread->misspeculating(), as it's never actually misspeculating.
--HG--
extra : convert_revision : 86574d684770fac9b480475acca048ea418cdac3
cpu/o3/alpha_dyn_inst.hh:
Set the instResult using a function on the base dyn inst.
cpu/o3/bpred_unit_impl.hh:
Don't need to reset the state.
cpu/o3/commit_impl.hh:
Mark instructions as completed.
Wait until all stores are written back to handle a fault.
cpu/o3/cpu.cc:
Clear instruction lists when switching out.
cpu/o3/lsq_unit.hh:
Allow wbEvent to be set externally.
cpu/o3/lsq_unit_impl.hh:
Mark instructions as completed properly. Also use events for writing back stores even if there is a hit in the dcache.
--HG--
extra : convert_revision : 172ad088b75ac31e848a5040633152b5c051444c
cpu/o3/alpha_cpu.hh:
Store conditionals should not write their data to memory if they failed.
cpu/o3/lsq_unit.hh:
Setup request parameters when they're needed.
--HG--
extra : convert_revision : d75cd7deda03584b7e25cb567e4d79032cac7118
arch/alpha/isa/decoder.isa:
Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model.
arch/alpha/isa/pal.isa:
Allow IPR instructions to have flags.
base/traceflags.py:
Include new trace flags from the two new CPU models.
cpu/SConscript:
Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next).
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Update to the BaseDynInst for the new models.
--HG--
extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
