gem5/src
Rekai Gonzalez-Alberquilla ad296b068c cpu: Fix the O3 CPU Drain
The drain did not wait until stages were ready again. Therefore, as a
result of messages in the TimeBuffer being drain, the state after the
drain was not consistent and asserts fired in some places when the
draining happened after a stage got blocked, but before the notification
arrived to the previous stages.

Change-Id: Ib50b3b40b7f745b62c1eba2931dec76860824c71
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-09-22 10:49:10 +01:00
..
arch hsail: Fix disassembly of load instruction with 3 destination operands 2016-09-16 12:36:20 -04:00
base base: Add total() to Vector2D stat 2016-07-21 17:19:15 +01:00
cpu cpu: Fix the O3 CPU Drain 2016-09-22 10:49:10 +01:00
dev dev: Add a DmaCallback class to DmaDevice 2016-09-13 23:14:24 -04:00
doc sim: Adding support for power models 2016-06-06 17:16:44 +01:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
gpu-compute gpu-compute: fix typo in GPUDispatcher 2016-09-16 14:47:19 -04:00
kern kern, arm: Dump dmesg on kernel panic/oops 2016-06-20 14:39:49 +01:00
mem cpu, mem, sim: Change how KVM maps memory 2016-08-22 11:41:05 -04:00
proto cpu: Support virtual addr in elastic traces 2015-12-07 16:42:16 -06:00
python base: eliminate ipython warning 2016-09-15 18:21:38 +01:00
sim sim: Refactor quiesce and remove FS asserts 2016-09-13 23:17:42 -04:00
unittest style: remove trailing whitespace 2016-02-06 17:21:18 -08:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript scons: Track swig packages when loading embedded swig code 2016-06-28 03:50:00 -04:00