89ea323250
Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
223 lines
24 KiB
Text
223 lines
24 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1674592 # Simulator instruction rate (inst/s)
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host_mem_usage 210700 # Number of bytes of host memory used
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host_seconds 238.07 # Real time elapsed on the host
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host_tick_rate 2383160323 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 398664609 # Number of instructions simulated
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sim_seconds 0.567352 # Number of seconds simulated
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sim_ticks 567351850000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 48286000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 45436000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 73517416 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 185584000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 3314 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 175642000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 3314 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 54847.560976 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 168270956 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 233870000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 4264 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 221078000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 4264 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 54847.560976 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 168270956 # number of overall hits
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system.cpu.dcache.overall_miss_latency 233870000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 4264 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 221078000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 4264 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 764 # number of replacements
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system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 3288.899192 # Cycle average of tags in use
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system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 625 # number of writebacks
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system.cpu.dtb.accesses 168275276 # DTB accesses
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system.cpu.dtb.acv 0 # DTB access violations
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system.cpu.dtb.hits 168275220 # DTB hits
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system.cpu.dtb.misses 56 # DTB misses
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system.cpu.dtb.read_accesses 94754511 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 94754490 # DTB read hits
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system.cpu.dtb.read_misses 21 # DTB read misses
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system.cpu.dtb.write_accesses 73520765 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 73520730 # DTB write hits
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system.cpu.dtb.write_misses 35 # DTB write misses
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system.cpu.icache.ReadReq_accesses 398664666 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 50648.516199 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 398660993 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 186032000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 175013000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 50648.516199 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
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system.cpu.icache.demand_hits 398660993 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 186032000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
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system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 175013000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 398660993 # number of overall hits
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system.cpu.icache.overall_miss_latency 186032000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
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system.cpu.icache.overall_misses 3673 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 175013000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 1769 # number of replacements
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system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 1795.124700 # Cycle average of tags in use
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system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.itb.accesses 398664839 # ITB accesses
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system.cpu.itb.acv 0 # ITB acv
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system.cpu.itb.hits 398664666 # ITB hits
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system.cpu.itb.misses 173 # ITB misses
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system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 166504000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 3202 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 128080000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 3202 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 209976000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 112 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 5824000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4480000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits
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system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 0.120240 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 585 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 376480000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.925240 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 7240 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 289600000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.925240 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 7240 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 585 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 376480000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.925240 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 7240 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 289600000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.925240 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 7240 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.replacements 15 # number of replacements
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system.cpu.l2cache.sampled_refs 4491 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 3714.176115 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 540 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 0 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 1134703700 # number of cpu cycles simulated
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system.cpu.num_insts 398664609 # Number of instructions executed
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system.cpu.num_refs 174183455 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
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---------- End Simulation Statistics ----------
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