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gem5/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
Andreas Hansson 74553c7d3f stats: Update the stats to reflect bus and memory changes 
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
2013-05-30 12:54:18 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 0.147136 # Number of seconds simulated
sim_ticks 147135976000 # Number of ticks simulated
final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 662214 # Simulator instruction rate (inst/s)
host_op_rate 666963 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1075722156 # Simulator tick rate (ticks/s)
host_mem_usage 375060 # Number of bytes of host memory used
host_seconds 136.78 # Real time elapsed on the host
sim_insts 90576861 # Number of instructions simulated
sim_ops 91226312 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 944768 # Number of bytes read from this memory
system.physmem.bytes_read::total 981760 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 36992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 36992 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 251414 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 6421054 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6672467 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 251414 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 251414 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 251414 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 6421054 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6672467 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 6672467 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 792 # Transaction distribution
system.membus.trans_dist::ReadResp 792 # Transaction distribution
system.membus.trans_dist::ReadExReq 14548 # Transaction distribution
system.membus.trans_dist::ReadExResp 14548 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side 30680 # Packet count per connected master and slave (bytes)
system.membus.pkt_count 30680 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 981760 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size 981760 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 981760 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 15340000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 138060000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 294271952 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90576861 # Number of instructions committed
system.cpu.committedOps 91226312 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
system.cpu.num_func_calls 112245 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15549034 # number of instructions that are conditional controls
system.cpu.num_int_insts 72525674 # number of integer instructions
system.cpu.num_fp_insts 48 # number of float instructions
system.cpu.num_int_register_reads 464563355 # number of times the integer registers were read
system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
system.cpu.num_mem_refs 27318810 # number of memory refs
system.cpu.num_load_insts 22573966 # Number of load instructions
system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 294271952 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 2 # number of replacements
system.cpu.icache.tagsinuse 510.071144 # Cycle average of tags in use
system.cpu.icache.total_refs 107830172 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 180016.981636 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.249058 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 107830172 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 107830172 # number of overall hits
system.cpu.icache.overall_hits::total 107830172 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses
system.cpu.icache.overall_misses::total 599 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32063000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 32063000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 32063000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 32063000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 32063000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 32063000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 107830771 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 107830771 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 107830771 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53527.545910 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 53527.545910 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53527.545910 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 53527.545910 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53527.545910 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 53527.545910 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30865000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 30865000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30865000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 30865000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51527.545910 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 9565.271881 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1827177 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 15323 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 119.244078 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.270902 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.291909 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 942334 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 942334 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 932036 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 932057 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 932036 # number of overall hits
system.cpu.l2cache.overall_hits::total 932057 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 578 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 214 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 792 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 578 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 14762 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 15340 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 578 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 14762 # number of overall misses
system.cpu.l2cache.overall_misses::total 15340 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30056000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11128000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 41184000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 756496000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 756496000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 30056000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 767624000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 797680000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 30056000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 767624000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 797680000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 900788 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 942334 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 942334 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 946798 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 947397 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964942 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000238 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.000879 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964942 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015591 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015591 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 578 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 214 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 792 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 578 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 14762 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 578 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 14762 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23120000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8560000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 31680000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 581920000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 581920000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590480000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 613600000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23120000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590480000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 613600000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000238 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000879 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 942702 # number of replacements
system.cpu.dcache.tagsinuse 3565.217259 # Cycle average of tags in use
system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.870414 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 26337590 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26337590 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26337590 # number of overall hits
system.cpu.dcache.overall_hits::total 26337590 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 946798 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses
system.cpu.dcache.overall_misses::total 946798 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711445000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11711445000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1216933000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1216933000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 12928378000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 12928378000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 12928378000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 12928378000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 27284388 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 27284388 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 27284388 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27284388 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.039921 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.984570 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.984570 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26109.399472 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 26109.399472 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13654.842955 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13654.842955 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks
system.cpu.dcache.writebacks::total 942334 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900189 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 946798 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 821979690 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1198 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2835930 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 2837128 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 38336 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120904448 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 120942784 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 120942784 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
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