22c04190c6
This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap (and similar) abstractions, as these are no longer needed with gcc 4.7 and clang 3.1 as minimum compiler versions.
253 lines
8.3 KiB
C++
253 lines
8.3 KiB
C++
/*
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* Copyright (c) 2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* Copyright (c) 2010 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Nathan Binkert
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*/
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/* @file
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* User Console Definitions
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*/
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#ifndef __SIM_OBJECT_HH__
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#define __SIM_OBJECT_HH__
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#include <iostream>
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#include <list>
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#include <map>
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#include <string>
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#include <vector>
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#include "enums/MemoryMode.hh"
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#include "params/SimObject.hh"
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#include "sim/drain.hh"
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#include "sim/eventq_impl.hh"
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#include "sim/serialize.hh"
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class BaseCPU;
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class Event;
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class ProbeManager;
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/**
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* Abstract superclass for simulation objects. Represents things that
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* correspond to physical components and can be specified via the
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* config file (CPUs, caches, etc.).
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*
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* SimObject initialization is controlled by the instantiate method in
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* src/python/m5/simulate.py. There are slightly different
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* initialization paths when starting the simulation afresh and when
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* loading from a checkpoint. After instantiation and connecting
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* ports, simulate.py initializes the object using the following call
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* sequence:
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*
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* <ol>
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* <li>SimObject::init()
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* <li>SimObject::regStats()
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* <li><ul>
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* <li>SimObject::initState() if starting afresh.
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* <li>SimObject::loadState() if restoring from a checkpoint.
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* </ul>
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* <li>SimObject::resetStats()
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* <li>SimObject::startup()
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* <li>Drainable::drainResume() if resuming from a checkpoint.
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* </ol>
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*
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* @note Whenever a method is called on all objects in the simulator's
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* object tree (e.g., init(), startup(), or loadState()), a pre-order
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* depth-first traversal is performed (see descendants() in
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* SimObject.py). This has the effect of calling the method on the
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* parent node <i>before</i> its children.
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*/
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class SimObject : public EventManager, public Serializable, public Drainable
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{
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private:
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typedef std::vector<SimObject *> SimObjectList;
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/** List of all instantiated simulation objects. */
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static SimObjectList simObjectList;
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/** Manager coordinates hooking up probe points with listeners. */
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ProbeManager *probeManager;
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protected:
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/** Cached copy of the object parameters. */
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const SimObjectParams *_params;
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public:
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typedef SimObjectParams Params;
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const Params *params() const { return _params; }
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SimObject(const Params *_params);
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virtual ~SimObject();
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public:
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virtual const std::string name() const { return params()->name; }
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/**
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* init() is called after all C++ SimObjects have been created and
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* all ports are connected. Initializations that are independent
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* of unserialization but rely on a fully instantiated and
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* connected SimObject graph should be done here.
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*/
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virtual void init();
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/**
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* loadState() is called on each SimObject when restoring from a
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* checkpoint. The default implementation simply calls
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* unserialize() if there is a corresponding section in the
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* checkpoint. However, objects can override loadState() to get
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* other behaviors, e.g., doing other programmed initializations
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* after unserialize(), or complaining if no checkpoint section is
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* found.
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*
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* @param cp Checkpoint to restore the state from.
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*/
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virtual void loadState(CheckpointIn &cp);
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/**
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* initState() is called on each SimObject when *not* restoring
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* from a checkpoint. This provides a hook for state
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* initializations that are only required for a "cold start".
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*/
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virtual void initState();
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/**
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* Register statistics for this object.
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*/
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virtual void regStats();
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/**
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* Reset statistics associated with this object.
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*/
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virtual void resetStats();
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/**
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* Register probe points for this object.
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*/
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virtual void regProbePoints();
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/**
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* Register probe listeners for this object.
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*/
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virtual void regProbeListeners();
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/**
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* Get the probe manager for this object.
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*/
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ProbeManager *getProbeManager();
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/**
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* startup() is the final initialization call before simulation.
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* All state is initialized (including unserialized state, if any,
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* such as the curTick() value), so this is the appropriate place to
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* schedule initial event(s) for objects that need them.
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*/
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virtual void startup();
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/**
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* Provide a default implementation of the drain interface for
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* objects that don't need draining.
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*/
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DrainState drain() override { return DrainState::Drained; }
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/**
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* Write back dirty buffers to memory using functional writes.
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*
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* After returning, an object implementing this method should have
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* written all its dirty data back to memory. This method is
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* typically used to prepare a system with caches for
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* checkpointing.
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*/
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virtual void memWriteback() {};
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/**
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* Invalidate the contents of memory buffers.
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*
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* When the switching to hardware virtualized CPU models, we need
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* to make sure that we don't have any cached state in the system
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* that might become stale when we return. This method is used to
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* flush all such state back to main memory.
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*
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* @warn This does <i>not</i> cause any dirty state to be written
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* back to memory.
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*/
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virtual void memInvalidate() {};
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void serialize(CheckpointOut &cp) const override {};
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void unserialize(CheckpointIn &cp) override {};
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/**
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* Serialize all SimObjects in the system.
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*/
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static void serializeAll(CheckpointOut &cp);
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#ifdef DEBUG
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public:
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bool doDebugBreak;
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static void debugObjectBreak(const std::string &objs);
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#endif
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/**
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* Find the SimObject with the given name and return a pointer to
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* it. Primarily used for interactive debugging. Argument is
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* char* rather than std::string to make it callable from gdb.
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*/
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static SimObject *find(const char *name);
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};
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/**
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* Base class to wrap object resolving functionality.
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*
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* This can be provided to the serialization framework to allow it to
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* map object names onto C++ objects.
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*/
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class SimObjectResolver
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{
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public:
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virtual ~SimObjectResolver() { }
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// Find a SimObject given a full path name
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virtual SimObject *resolveSimObject(const std::string &name) = 0;
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};
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#ifdef DEBUG
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void debugObjectBreak(const char *objs);
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#endif
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#endif // __SIM_OBJECT_HH__
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