gem5/src/mem/cache/miss
Kevin Lim 047f77102b Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2

src/cpu/base_dyn_inst.hh:
    Hand merge.  Line is no longer needed because it's handled in the ISA.

--HG--
extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680
2007-03-23 13:20:19 -04:00
..
blocking_buffer.cc Make memory commands dense again to avoid cache stat table explosion. 2007-02-07 10:53:37 -08:00
blocking_buffer.hh Make memory commands dense again to avoid cache stat table explosion. 2007-02-07 10:53:37 -08:00
miss_buffer.cc Turn cache MissQueue/BlockingBuffer into virtual object 2006-12-04 09:10:53 -08:00
miss_buffer.hh Make memory commands dense again to avoid cache stat table explosion. 2007-02-07 10:53:37 -08:00
miss_queue.cc Merge ktlim@zizzer:/bk/newmem 2007-03-23 13:20:19 -04:00
miss_queue.hh Make memory commands dense again to avoid cache stat table explosion. 2007-02-07 10:53:37 -08:00
mshr.cc Move all of the parameters of the Root SimObject so they are 2007-03-06 11:13:43 -08:00
mshr.hh Make memory commands dense again to avoid cache stat table explosion. 2007-02-07 10:53:37 -08:00
mshr_queue.cc Make memory commands dense again to avoid cache stat table explosion. 2007-02-07 10:53:37 -08:00
mshr_queue.hh Make memory commands dense again to avoid cache stat table explosion. 2007-02-07 10:53:37 -08:00
SConscript Rework the way SCons recurses into subdirectories, making it 2007-03-10 23:00:54 -08:00