abc76f20cb
creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
323 lines
12 KiB
C++
323 lines
12 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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* Nathan Binkert
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*/
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/**
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* @file
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* Simobject instatiation of caches.
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*/
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#include <vector>
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// Must be included first to determine which caches we want
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#include "enums/Prefetch.hh"
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#include "mem/config/cache.hh"
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#include "mem/config/prefetch.hh"
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#include "mem/cache/base_cache.hh"
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#include "mem/cache/cache.hh"
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#include "mem/bus.hh"
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#include "mem/cache/coherence/coherence_protocol.hh"
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#include "params/BaseCache.hh"
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// Tag Templates
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#if defined(USE_CACHE_LRU)
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#include "mem/cache/tags/lru.hh"
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#endif
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#if defined(USE_CACHE_FALRU)
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#include "mem/cache/tags/fa_lru.hh"
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#endif
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#if defined(USE_CACHE_IIC)
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#include "mem/cache/tags/iic.hh"
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#endif
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#if defined(USE_CACHE_SPLIT)
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#include "mem/cache/tags/split.hh"
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#endif
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#if defined(USE_CACHE_SPLIT_LIFO)
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#include "mem/cache/tags/split_lifo.hh"
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#endif
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// Compression Templates
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#include "base/compression/null_compression.hh"
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#include "base/compression/lzss_compression.hh"
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// MissQueue Templates
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#include "mem/cache/miss/miss_queue.hh"
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#include "mem/cache/miss/blocking_buffer.hh"
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// Coherence Templates
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#include "mem/cache/coherence/uni_coherence.hh"
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#include "mem/cache/coherence/simple_coherence.hh"
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//Prefetcher Headers
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#if defined(USE_GHB)
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#include "mem/cache/prefetch/ghb_prefetcher.hh"
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#endif
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#if defined(USE_TAGGED)
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#include "mem/cache/prefetch/tagged_prefetcher.hh"
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#endif
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#if defined(USE_STRIDED)
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#include "mem/cache/prefetch/stride_prefetcher.hh"
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#endif
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using namespace std;
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using namespace TheISA;
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#define BUILD_CACHE(TAGS, tags, c) \
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do { \
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BasePrefetcher *pf; \
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if (prefetch_policy == Enums::tagged) { \
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BUILD_TAGGED_PREFETCHER(TAGS); \
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} \
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else if (prefetch_policy == Enums::stride) { \
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BUILD_STRIDED_PREFETCHER(TAGS); \
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} \
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else if (prefetch_policy == Enums::ghb) { \
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BUILD_GHB_PREFETCHER(TAGS); \
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} \
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else { \
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BUILD_NULL_PREFETCHER(TAGS); \
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} \
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Cache<TAGS, c>::Params params(tags, mq, coh, base_params, \
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pf, prefetch_access, latency, \
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true, \
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store_compressed, \
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adaptive_compression, \
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compressed_bus, \
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compAlg, compression_latency, \
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prefetch_miss); \
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Cache<TAGS, c> *retval = \
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new Cache<TAGS, c>(name, params); \
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return retval; \
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} while (0)
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#define BUILD_CACHE_PANIC(x) do { \
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panic("%s not compiled into M5", x); \
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} while (0)
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#define BUILD_COMPRESSED_CACHE(TAGS, tags, c) \
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do { \
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CompressionAlgorithm *compAlg; \
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if (compressed_bus || store_compressed) { \
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compAlg = new LZSSCompression(); \
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} else { \
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compAlg = new NullCompression(); \
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} \
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BUILD_CACHE(TAGS, tags, c); \
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} while (0)
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#if defined(USE_CACHE_FALRU)
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#define BUILD_FALRU_CACHE(c) do { \
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FALRU *tags = new FALRU(block_size, size, latency); \
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BUILD_COMPRESSED_CACHE(FALRU, tags, c); \
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} while (0)
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#else
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#define BUILD_FALRU_CACHE(c) BUILD_CACHE_PANIC("falru cache")
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#endif
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#if defined(USE_CACHE_LRU)
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#define BUILD_LRU_CACHE(c) do { \
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LRU *tags = new LRU(numSets, block_size, assoc, latency); \
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BUILD_COMPRESSED_CACHE(LRU, tags, c); \
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} while (0)
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#else
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#define BUILD_LRU_CACHE(c) BUILD_CACHE_PANIC("lru cache")
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#endif
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#if defined(USE_CACHE_SPLIT)
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#define BUILD_SPLIT_CACHE(c) do { \
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Split *tags = new Split(numSets, block_size, assoc, split_size, lifo, \
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two_queue, latency); \
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BUILD_COMPRESSED_CACHE(Split, tags, c); \
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} while (0)
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#else
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#define BUILD_SPLIT_CACHE(c) BUILD_CACHE_PANIC("split cache")
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#endif
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#if defined(USE_CACHE_SPLIT_LIFO)
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#define BUILD_SPLIT_LIFO_CACHE(c) do { \
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SplitLIFO *tags = new SplitLIFO(block_size, size, assoc, \
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latency, two_queue, -1); \
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BUILD_COMPRESSED_CACHE(SplitLIFO, tags, c); \
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} while (0)
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#else
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#define BUILD_SPLIT_LIFO_CACHE(c) BUILD_CACHE_PANIC("lifo cache")
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#endif
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#if defined(USE_CACHE_IIC)
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#define BUILD_IIC_CACHE(c) do { \
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IIC *tags = new IIC(iic_params); \
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BUILD_COMPRESSED_CACHE(IIC, tags, c); \
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} while (0)
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#else
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#define BUILD_IIC_CACHE(c) BUILD_CACHE_PANIC("iic")
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#endif
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#define BUILD_CACHES(c) do { \
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if (repl == NULL) { \
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if (numSets == 1) { \
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BUILD_FALRU_CACHE(c); \
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} else { \
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if (split == true) { \
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BUILD_SPLIT_CACHE(c); \
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} else if (lifo == true) { \
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BUILD_SPLIT_LIFO_CACHE(c); \
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} else { \
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BUILD_LRU_CACHE(c); \
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} \
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} \
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} else { \
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BUILD_IIC_CACHE(c); \
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} \
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} while (0)
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#define BUILD_COHERENCE(b) do { \
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if (protocol == NULL) { \
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UniCoherence *coh = new UniCoherence(); \
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BUILD_CACHES(UniCoherence); \
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} else { \
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SimpleCoherence *coh = new SimpleCoherence(protocol); \
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BUILD_CACHES(SimpleCoherence); \
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} \
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} while (0)
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#if defined(USE_TAGGED)
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#define BUILD_TAGGED_PREFETCHER(t) \
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pf = new TaggedPrefetcher(prefetcher_size, \
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!prefetch_past_page, \
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prefetch_serial_squash, \
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prefetch_cache_check_push, \
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prefetch_data_accesses_only, \
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prefetch_latency, \
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prefetch_degree)
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#else
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#define BUILD_TAGGED_PREFETCHER(t) BUILD_CACHE_PANIC("Tagged Prefetcher")
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#endif
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#if defined(USE_STRIDED)
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#define BUILD_STRIDED_PREFETCHER(t) \
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pf = new StridePrefetcher(prefetcher_size, \
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!prefetch_past_page, \
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prefetch_serial_squash, \
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prefetch_cache_check_push, \
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prefetch_data_accesses_only, \
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prefetch_latency, \
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prefetch_degree, \
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prefetch_use_cpu_id)
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#else
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#define BUILD_STRIDED_PREFETCHER(t) BUILD_CACHE_PANIC("Stride Prefetcher")
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#endif
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#if defined(USE_GHB)
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#define BUILD_GHB_PREFETCHER(t) \
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pf = new GHBPrefetcher(prefetcher_size, \
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!prefetch_past_page, \
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prefetch_serial_squash, \
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prefetch_cache_check_push, \
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prefetch_data_accesses_only, \
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prefetch_latency, \
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prefetch_degree, \
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prefetch_use_cpu_id)
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#else
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#define BUILD_GHB_PREFETCHER(t) BUILD_CACHE_PANIC("GHB Prefetcher")
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#endif
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#if defined(USE_TAGGED)
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#define BUILD_NULL_PREFETCHER(t) \
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pf = new TaggedPrefetcher(prefetcher_size, \
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!prefetch_past_page, \
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prefetch_serial_squash, \
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prefetch_cache_check_push, \
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prefetch_data_accesses_only, \
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prefetch_latency, \
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prefetch_degree)
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#else
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#define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
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#endif
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BaseCache *
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BaseCacheParams::create()
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{
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int numSets = size / (assoc * block_size);
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if (subblock_size == 0) {
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subblock_size = block_size;
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}
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// Build BaseCache param object
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BaseCache::Params base_params(addr_range, latency,
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block_size, max_miss_count);
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//Warnings about prefetcher policy
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if (prefetch_policy == Enums::none) {
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if (prefetch_miss || prefetch_access)
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panic("With no prefetcher, you shouldn't prefetch from"
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" either miss or access stream\n");
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}
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if (prefetch_policy == Enums::tagged || prefetch_policy == Enums::stride ||
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prefetch_policy == Enums::ghb) {
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if (!prefetch_miss && !prefetch_access)
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warn("With this prefetcher you should chose a prefetch"
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" stream (miss or access)\nNo Prefetching will occur\n");
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if (prefetch_miss && prefetch_access)
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panic("Can't do prefetches from both miss and access stream");
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}
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#if defined(USE_CACHE_IIC)
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// Build IIC params
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IIC::Params iic_params;
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iic_params.size = size;
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iic_params.numSets = numSets;
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iic_params.blkSize = block_size;
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iic_params.assoc = assoc;
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iic_params.hashDelay = hash_delay;
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iic_params.hitLatency = latency;
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iic_params.rp = repl;
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iic_params.subblockSize = subblock_size;
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#else
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const void *repl = NULL;
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#endif
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if (mshrs == 1 /*|| out_bus->doEvents() == false*/) {
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BlockingBuffer *mq = new BlockingBuffer(true);
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BUILD_COHERENCE(BlockingBuffer);
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} else {
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MissQueue *mq = new MissQueue(mshrs, tgts_per_mshr, write_buffers,
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true, prefetch_miss);
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BUILD_COHERENCE(MissQueue);
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}
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return NULL;
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}
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