abc76f20cb
creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
512 lines
14 KiB
C++
512 lines
14 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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*/
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#include "arch/utility.hh"
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#include "arch/faults.hh"
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#include "base/cprintf.hh"
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#include "base/inifile.hh"
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#include "base/loader/symtab.hh"
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#include "base/misc.hh"
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#include "base/pollevent.hh"
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#include "base/range.hh"
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#include "base/stats/events.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/profile.hh"
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#include "cpu/simple/base.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/smt.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "mem/packet.hh"
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#include "sim/byteswap.hh"
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#include "sim/debug.hh"
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#include "sim/host.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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#include "sim/system.hh"
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#if FULL_SYSTEM
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#include "arch/kernel_stats.hh"
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#include "arch/stacktrace.hh"
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#include "arch/tlb.hh"
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#include "arch/vtophys.hh"
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#include "base/remote_gdb.hh"
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#else // !FULL_SYSTEM
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#include "mem/mem_object.hh"
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#endif // FULL_SYSTEM
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using namespace std;
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using namespace TheISA;
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BaseSimpleCPU::BaseSimpleCPU(Params *p)
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: BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
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{
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#if FULL_SYSTEM
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thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
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#else
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thread = new SimpleThread(this, /* thread_num */ 0, p->process,
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/* asid */ 0);
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#endif // !FULL_SYSTEM
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thread->setStatus(ThreadContext::Unallocated);
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tc = thread->getTC();
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numInst = 0;
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startNumInst = 0;
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numLoad = 0;
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startNumLoad = 0;
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lastIcacheStall = 0;
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lastDcacheStall = 0;
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threadContexts.push_back(tc);
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fetchOffset = 0;
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stayAtPC = false;
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}
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BaseSimpleCPU::~BaseSimpleCPU()
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{
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}
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void
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BaseSimpleCPU::deallocateContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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void
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BaseSimpleCPU::haltContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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void
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BaseSimpleCPU::regStats()
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{
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using namespace Stats;
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BaseCPU::regStats();
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numInsts
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.name(name() + ".num_insts")
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.desc("Number of instructions executed")
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;
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numMemRefs
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.name(name() + ".num_refs")
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.desc("Number of memory references")
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;
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notIdleFraction
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.name(name() + ".not_idle_fraction")
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.desc("Percentage of non-idle cycles")
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;
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idleFraction
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.name(name() + ".idle_fraction")
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.desc("Percentage of idle cycles")
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;
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icacheStallCycles
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.name(name() + ".icache_stall_cycles")
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.desc("ICache total stall cycles")
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.prereq(icacheStallCycles)
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;
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dcacheStallCycles
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.name(name() + ".dcache_stall_cycles")
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.desc("DCache total stall cycles")
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.prereq(dcacheStallCycles)
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;
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icacheRetryCycles
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.name(name() + ".icache_retry_cycles")
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.desc("ICache total retry cycles")
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.prereq(icacheRetryCycles)
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;
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dcacheRetryCycles
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.name(name() + ".dcache_retry_cycles")
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.desc("DCache total retry cycles")
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.prereq(dcacheRetryCycles)
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;
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idleFraction = constant(1.0) - notIdleFraction;
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}
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void
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BaseSimpleCPU::resetStats()
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{
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// startNumInst = numInst;
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// notIdleFraction = (_status != Idle);
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}
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void
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BaseSimpleCPU::serialize(ostream &os)
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{
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BaseCPU::serialize(os);
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// SERIALIZE_SCALAR(inst);
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nameOut(os, csprintf("%s.xc.0", name()));
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thread->serialize(os);
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}
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void
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BaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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BaseCPU::unserialize(cp, section);
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// UNSERIALIZE_SCALAR(inst);
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thread->unserialize(cp, csprintf("%s.xc.0", section));
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}
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void
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change_thread_state(int thread_number, int activate, int priority)
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{
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}
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Fault
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BaseSimpleCPU::copySrcTranslate(Addr src)
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{
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#if 0
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static bool no_warn = true;
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int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
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// Only support block sizes of 64 atm.
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assert(blk_size == 64);
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int offset = src & (blk_size - 1);
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// Make sure block doesn't span page
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if (no_warn &&
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(src & PageMask) != ((src + blk_size) & PageMask) &&
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(src >> 40) != 0xfffffc) {
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warn("Copied block source spans pages %x.", src);
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no_warn = false;
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}
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memReq->reset(src & ~(blk_size - 1), blk_size);
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// translate to physical address
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Fault fault = thread->translateDataReadReq(req);
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if (fault == NoFault) {
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thread->copySrcAddr = src;
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thread->copySrcPhysAddr = memReq->paddr + offset;
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} else {
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assert(!fault->isAlignmentFault());
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thread->copySrcAddr = 0;
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thread->copySrcPhysAddr = 0;
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}
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return fault;
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#else
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return NoFault;
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#endif
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}
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Fault
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BaseSimpleCPU::copy(Addr dest)
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{
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#if 0
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static bool no_warn = true;
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int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
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// Only support block sizes of 64 atm.
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assert(blk_size == 64);
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uint8_t data[blk_size];
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//assert(thread->copySrcAddr);
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int offset = dest & (blk_size - 1);
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// Make sure block doesn't span page
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if (no_warn &&
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(dest & PageMask) != ((dest + blk_size) & PageMask) &&
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(dest >> 40) != 0xfffffc) {
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no_warn = false;
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warn("Copied block destination spans pages %x. ", dest);
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}
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memReq->reset(dest & ~(blk_size -1), blk_size);
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// translate to physical address
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Fault fault = thread->translateDataWriteReq(req);
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if (fault == NoFault) {
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Addr dest_addr = memReq->paddr + offset;
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// Need to read straight from memory since we have more than 8 bytes.
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memReq->paddr = thread->copySrcPhysAddr;
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thread->mem->read(memReq, data);
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memReq->paddr = dest_addr;
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thread->mem->write(memReq, data);
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if (dcacheInterface) {
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memReq->cmd = Copy;
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memReq->completionEvent = NULL;
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memReq->paddr = thread->copySrcPhysAddr;
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memReq->dest = dest_addr;
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memReq->size = 64;
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memReq->time = curTick;
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memReq->flags &= ~INST_READ;
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dcacheInterface->access(memReq);
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}
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}
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else
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assert(!fault->isAlignmentFault());
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return fault;
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#else
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panic("copy not implemented");
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return NoFault;
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#endif
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}
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#if FULL_SYSTEM
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Addr
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BaseSimpleCPU::dbg_vtophys(Addr addr)
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{
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return vtophys(tc, addr);
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}
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#endif // FULL_SYSTEM
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#if FULL_SYSTEM
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void
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BaseSimpleCPU::post_interrupt(int int_num, int index)
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{
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BaseCPU::post_interrupt(int_num, index);
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if (thread->status() == ThreadContext::Suspended) {
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DPRINTF(Quiesce,"Suspended Processor awoke\n");
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thread->activate();
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}
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}
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#endif // FULL_SYSTEM
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void
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BaseSimpleCPU::checkForInterrupts()
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{
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#if FULL_SYSTEM
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if (check_interrupts(tc)) {
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Fault interrupt = interrupts.getInterrupt(tc);
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if (interrupt != NoFault) {
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interrupts.updateIntrInfo(tc);
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interrupt->invoke(tc);
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}
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}
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#endif
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}
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Fault
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BaseSimpleCPU::setupFetchRequest(Request *req)
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{
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Addr threadPC = thread->readPC();
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// set up memory request for instruction fetch
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#if ISA_HAS_DELAY_SLOT
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DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
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thread->readNextPC(),thread->readNextNPC());
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#else
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DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC,
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thread->readNextPC());
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#endif
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Addr fetchPC = (threadPC & PCMask) + fetchOffset;
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req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC);
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Fault fault = thread->translateInstReq(req);
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return fault;
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}
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void
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BaseSimpleCPU::preExecute()
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{
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// maintain $r0 semantics
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thread->setIntReg(ZeroReg, 0);
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#if THE_ISA == ALPHA_ISA
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thread->setFloatReg(ZeroReg, 0.0);
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#endif // ALPHA_ISA
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// keep an instruction count
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numInst++;
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numInsts++;
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thread->funcExeInst++;
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// check for instruction-count-based events
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comInstEventQueue[0]->serviceEvents(numInst);
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// decode the instruction
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inst = gtoh(inst);
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//If we're not in the middle of a macro instruction
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if (!curMacroStaticInst) {
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StaticInstPtr instPtr = NULL;
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//Predecode, ie bundle up an ExtMachInst
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//This should go away once the constructor can be set up properly
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predecoder.setTC(thread->getTC());
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//If more fetch data is needed, pass it in.
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Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset;
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//if(predecoder.needMoreBytes())
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predecoder.moreBytes(thread->readPC(), fetchPC, inst);
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//else
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// predecoder.process();
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//If an instruction is ready, decode it. Otherwise, we'll have to
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//fetch beyond the MachInst at the current pc.
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if (predecoder.extMachInstReady()) {
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#if THE_ISA == X86_ISA
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thread->setNextPC(thread->readPC() + predecoder.getInstSize());
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#endif // X86_ISA
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stayAtPC = false;
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instPtr = StaticInst::decode(predecoder.getExtMachInst(),
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thread->readPC());
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} else {
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stayAtPC = true;
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fetchOffset += sizeof(MachInst);
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}
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//If we decoded an instruction and it's microcoded, start pulling
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//out micro ops
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if (instPtr && instPtr->isMacroop()) {
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curMacroStaticInst = instPtr;
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curStaticInst = curMacroStaticInst->
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fetchMicroop(thread->readMicroPC());
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} else {
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curStaticInst = instPtr;
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}
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} else {
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//Read the next micro op from the macro op
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curStaticInst = curMacroStaticInst->
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fetchMicroop(thread->readMicroPC());
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}
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//If we decoded an instruction this "tick", record information about it.
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if(curStaticInst)
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{
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#if TRACING_ON
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traceData = Trace::getInstRecord(curTick, tc, curStaticInst,
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thread->readPC());
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DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
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curStaticInst->getName(), curStaticInst->machInst);
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#endif // TRACING_ON
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#if FULL_SYSTEM
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thread->setInst(inst);
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#endif // FULL_SYSTEM
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}
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}
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void
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BaseSimpleCPU::postExecute()
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{
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#if FULL_SYSTEM
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if (thread->profile) {
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bool usermode = TheISA::inUserMode(tc);
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thread->profilePC = usermode ? 1 : thread->readPC();
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StaticInstPtr si(inst, thread->readPC());
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ProfileNode *node = thread->profile->consume(tc, si);
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if (node)
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thread->profileNode = node;
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}
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#endif
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if (curStaticInst->isMemRef()) {
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numMemRefs++;
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}
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if (curStaticInst->isLoad()) {
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++numLoad;
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comLoadEventQueue[0]->serviceEvents(numLoad);
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}
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traceFunctions(thread->readPC());
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if (traceData) {
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traceData->dump();
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delete traceData;
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traceData = NULL;
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}
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}
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void
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BaseSimpleCPU::advancePC(Fault fault)
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{
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//Since we're moving to a new pc, zero out the offset
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fetchOffset = 0;
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if (fault != NoFault) {
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curMacroStaticInst = StaticInst::nullStaticInstPtr;
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fault->invoke(tc);
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thread->setMicroPC(0);
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thread->setNextMicroPC(1);
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} else {
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//If we're at the last micro op for this instruction
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if (curStaticInst && curStaticInst->isLastMicroop()) {
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//We should be working with a macro op
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assert(curMacroStaticInst);
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//Close out this macro op, and clean up the
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//microcode state
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curMacroStaticInst = StaticInst::nullStaticInstPtr;
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thread->setMicroPC(0);
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thread->setNextMicroPC(1);
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}
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//If we're still in a macro op
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if (curMacroStaticInst) {
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//Advance the micro pc
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thread->setMicroPC(thread->readNextMicroPC());
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//Advance the "next" micro pc. Note that there are no delay
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//slots, and micro ops are "word" addressed.
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thread->setNextMicroPC(thread->readNextMicroPC() + 1);
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} else {
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// go to the next instruction
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thread->setPC(thread->readNextPC());
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thread->setNextPC(thread->readNextNPC());
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thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
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assert(thread->readNextPC() != thread->readNextNPC());
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}
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}
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#if FULL_SYSTEM
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Addr oldpc;
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do {
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oldpc = thread->readPC();
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system->pcEventQueue.service(tc);
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} while (oldpc != thread->readPC());
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#endif
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}
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