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gem5/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
Brad Beckmann ab2f864af2 m5: Regression Tester Update 
This patch includes the necessary regression updates to test the new ruby
configuration system.  The patch includes support for multiple ruby protocols
and adds the ruby random tester.  The patch removes atomic mode test for
ruby since ruby does not support atomic mode acceses.  These tests can be
added back in when ruby supports atomic mode for real.

--HG--
rename : tests/quick/50.memtest/test.py => tests/quick/60.rubytest/test.py
2010-01-29 20:29:40 -08:00

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================ Begin RubySystem Configuration Print ================
RubySystem config:
random_seed: 1234
randomization: 1
cycle_period: 1
block_size_bytes: 64
block_size_bits: 6
memory_size_bytes: 134217728
memory_size_bits: 27
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology:
virtual_net_0: active, unordered
virtual_net_1: active, unordered
virtual_net_2: active, unordered
virtual_net_3: inactive
virtual_net_4: inactive
virtual_net_5: inactive
virtual_net_6: inactive
virtual_net_7: inactive
virtual_net_8: inactive
virtual_net_9: inactive
Profiler Configuration
----------------------
periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Jan/27/2010 22:07:37
Profiler Stats
--------------
Elapsed_time_in_seconds: 2
Elapsed_time_in_minutes: 0.0333333
Elapsed_time_in_hours: 0.000555556
Elapsed_time_in_days: 2.31481e-05
Virtual_time_in_seconds: 1.4
Virtual_time_in_minutes: 0.0233333
Virtual_time_in_hours: 0.000388889
Virtual_time_in_days: 1.62037e-05
Ruby_current_time: 357031
Ruby_start_time: 0
Ruby_cycles: 357031
mbytes_resident: 31.0938
mbytes_total: 31.1016
resident_ratio: 1
Total_misses: 0
total_misses: 0 [ 0 ]
user_misses: 0 [ 0 ]
supervisor_misses: 0 [ 0 ]
ruby_cycles_executed: 357032 [ 357032 ]
transactions_started: 0 [ 0 ]
transactions_ended: 0 [ 0 ]
cycles_per_transaction: 0 [ 0 ]
misses_per_transaction: 0 [ 0 ]
Busy Controller Counts:
L1Cache-0:0
L2Cache-0:0
Directory-0:0
Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 970 average: 15.8278 | standard deviation: 1.13986 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 48 908 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 256 max: 34787 count: 954 average: 5860.09 | standard deviation: 7881.77 | 94 12 70 81 75 77 58 51 39 26 24 21 14 6 9 8 5 4 5 6 9 4 5 3 5 4 2 1 1 5 1 2 1 0 0 1 1 1 1 0 0 2 3 5 3 1 1 1 2 2 2 1 5 1 4 6 2 2 5 8 1 6 6 4 2 3 8 3 1 3 5 8 3 5 4 1 5 6 6 4 6 3 6 2 3 5 2 1 3 1 4 2 1 1 4 2 2 2 3 3 1 2 4 3 0 1 0 2 3 0 1 0 1 0 1 1 0 0 1 0 0 2 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_2: [binsize: 256 max: 26521 count: 100 average: 5073.78 | standard deviation: 7357.14 | 10 1 5 11 11 3 3 4 7 6 6 4 3 0 1 0 2 1 0 2 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 2 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_3: [binsize: 256 max: 34787 count: 854 average: 5952.16 | standard deviation: 7939.9 | 84 11 65 70 64 74 55 47 32 20 18 17 11 6 8 8 3 3 5 4 9 4 5 3 3 4 2 1 1 5 1 2 1 0 0 1 1 1 1 0 0 1 3 5 3 1 1 1 2 2 2 1 5 1 3 5 2 1 5 8 1 5 6 4 2 3 8 3 1 2 5 8 2 5 4 0 5 5 6 4 6 1 6 2 2 4 2 1 3 1 4 2 1 1 3 2 2 2 2 3 1 1 3 2 0 1 0 2 3 0 1 0 1 0 1 1 0 0 1 0 0 2 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Request vs. RubySystem State Profile
--------------------------------
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Message Delayed Cycles
----------------------
Total_delay_cycles: [binsize: 32 max: 1590 count: 6452 average: 19.6141 | standard deviation: 106.746 | 6116 4 30 74 2 5 34 6 4 19 14 1 15 14 3 9 18 2 3 14 16 2 6 11 2 0 7 5 1 2 2 0 0 3 0 2 0 0 0 1 0 0 4 0 0 0 0 0 0 1 ]
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 3918 average: 0 | standard deviation: 0 | 3918 ]
virtual_network_0_delay_cycles: [binsize: 32 max: 1590 count: 2534 average: 49.9408 | standard deviation: 165.845 | 2198 4 30 74 2 5 34 6 4 19 14 1 15 14 3 9 18 2 3 14 16 2 6 11 2 0 7 5 1 2 2 0 0 3 0 2 0 0 0 1 0 0 4 0 0 0 0 0 0 1 ]
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 531 average: 0 | standard deviation: 0 | 531 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 3387 average: 0 | standard deviation: 0 | 3387 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
user_time: 1
system_time: 0
page_reclaims: 6770
page_faults: 1936
swaps: 0
block_inputs: 0
block_outputs: 0
Network Stats
-------------
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0.106988
links_utilized_percent_switch_0_link_0: 0.0301689 bw: 640000 base_latency: 1
links_utilized_percent_switch_0_link_1: 0.183808 bw: 160000 base_latency: 1
outgoing_messages_switch_0_link_0_Request_Control: 531 4248 [ 531 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 862 62064 [ 0 862 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Response_Control: 328 2624 [ 0 328 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Control: 863 6904 [ 863 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Response_Control: 866 6928 [ 0 4 862 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Data: 1257 90504 [ 730 527 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Control: 83 664 [ 83 0 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 0.151261
links_utilized_percent_switch_1_link_0: 0.0751615 bw: 640000 base_latency: 1
links_utilized_percent_switch_1_link_1: 0.227361 bw: 160000 base_latency: 1
outgoing_messages_switch_1_link_0_Control: 862 6896 [ 862 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Response_Data: 835 60120 [ 0 835 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Response_Control: 1695 13560 [ 0 835 860 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Data: 1257 90504 [ 730 527 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Control: 83 664 [ 83 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Control: 835 6680 [ 835 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Request_Control: 531 4248 [ 531 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 1606 115632 [ 0 1606 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Control: 415 3320 [ 0 415 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 0.071776
links_utilized_percent_switch_2_link_0: 0.0266714 bw: 640000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0.116881 bw: 160000 base_latency: 1
outgoing_messages_switch_2_link_0_Control: 835 6680 [ 835 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 744 53568 [ 0 744 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Response_Control: 87 696 [ 0 87 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Response_Data: 835 60120 [ 0 835 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Response_Control: 831 6648 [ 0 831 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_3_inlinks: 3
switch_3_outlinks: 3
links_utilized_percent_switch_3: 0.176007
links_utilized_percent_switch_3_link_0: 0.120676 bw: 160000 base_latency: 1
links_utilized_percent_switch_3_link_1: 0.30066 bw: 160000 base_latency: 1
links_utilized_percent_switch_3_link_2: 0.106685 bw: 160000 base_latency: 1
outgoing_messages_switch_3_link_0_Request_Control: 531 4248 [ 531 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_0_Response_Data: 862 62064 [ 0 862 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_0_Response_Control: 328 2624 [ 0 328 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Control: 863 6904 [ 863 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Response_Data: 835 60120 [ 0 835 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Response_Control: 1695 13560 [ 0 835 860 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Writeback_Data: 1257 90504 [ 730 527 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_1_Writeback_Control: 83 664 [ 83 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Control: 835 6680 [ 835 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Response_Data: 744 53568 [ 0 744 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Response_Control: 87 696 [ 0 87 0 0 0 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
--- L1Cache 0 ---
- Event Counts -
Load 100
Ifetch 0
Store 856
Inv 531
L1_Replacement 507964
Fwd_GETX 0
Fwd_GETS 0
Fwd_GET_INSTR 0
Data 0
Data_Exclusive 90
DataS_fromL1 0
Data_all_Acks 772
Ack 0
Ack_all 0
WB_Ack 328
- Transitions -
NP Load 90
NP Ifetch 0 <--
NP Store 774
NP Inv 0 <--
NP L1_Replacement 0 <--
I Load 0 <--
I Ifetch 0 <--
I Store 0 <--
I Inv 0 <--
I L1_Replacement 46
S Load 0 <--
S Ifetch 0 <--
S Store 0 <--
S Inv 0 <--
S L1_Replacement 0 <--
E Load 0 <--
E Ifetch 0 <--
E Store 1
E Inv 4
E L1_Replacement 85
E Fwd_GETX 0 <--
E Fwd_GETS 0 <--
E Fwd_GET_INSTR 0 <--
M Load 10
M Ifetch 0 <--
M Store 81
M Inv 42
M L1_Replacement 730
M Fwd_GETX 0 <--
M Fwd_GETS 0 <--
M Fwd_GET_INSTR 0 <--
IS Load 0 <--
IS Ifetch 0 <--
IS Store 0 <--
IS Inv 0 <--
IS L1_Replacement 54611
IS Data_Exclusive 90
IS DataS_fromL1 0 <--
IS Data_all_Acks 0 <--
IM Load 0 <--
IM Ifetch 0 <--
IM Store 0 <--
IM Inv 0 <--
IM L1_Replacement 452492
IM Data 0 <--
IM Data_all_Acks 772
IM Ack 0 <--
SM Load 0 <--
SM Ifetch 0 <--
SM Store 0 <--
SM Inv 0 <--
SM L1_Replacement 0 <--
SM Ack 0 <--
SM Ack_all 0 <--
IS_I Load 0 <--
IS_I Ifetch 0 <--
IS_I Store 0 <--
IS_I Inv 0 <--
IS_I L1_Replacement 0 <--
IS_I Data_Exclusive 0 <--
IS_I DataS_fromL1 0 <--
IS_I Data_all_Acks 0 <--
M_I Load 0 <--
M_I Ifetch 0 <--
M_I Store 0 <--
M_I Inv 485
M_I L1_Replacement 0 <--
M_I Fwd_GETX 0 <--
M_I Fwd_GETS 0 <--
M_I Fwd_GET_INSTR 0 <--
M_I WB_Ack 328
E_I Load 0 <--
E_I Ifetch 0 <--
E_I Store 0 <--
E_I L1_Replacement 0 <--
Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
--- L2Cache 0 ---
- Event Counts -
L1_GET_INSTR 0
L1_GETS 102
L1_GETX 773
L1_UPGRADE 0
L1_PUTX 513
L1_PUTX_old 484
Fwd_L1_GETX 0
Fwd_L1_GETS 0
Fwd_L1_GET_INSTR 0
L2_Replacement 259
L2_Replacement_clean 13081
Mem_Data 835
Mem_Ack 831
WB_Data 485
WB_Data_clean 42
Ack 0
Ack_all 4
Unblock 0
Unblock_Cancel 0
Exclusive_Unblock 860
MEM_Inv 0
- Transitions -
NP L1_GET_INSTR 0 <--
NP L1_GETS 89
NP L1_GETX 746
NP L1_PUTX 0 <--
NP L1_PUTX_old 104
SS L1_GET_INSTR 0 <--
SS L1_GETS 0 <--
SS L1_GETX 0 <--
SS L1_UPGRADE 0 <--
SS L1_PUTX 0 <--
SS L1_PUTX_old 0 <--
SS L2_Replacement 0 <--
SS L2_Replacement_clean 0 <--
SS MEM_Inv 0 <--
M L1_GET_INSTR 0 <--
M L1_GETS 1
M L1_GETX 26
M L1_PUTX 0 <--
M L1_PUTX_old 0 <--
M L2_Replacement 259
M L2_Replacement_clean 41
M MEM_Inv 0 <--
MT L1_GET_INSTR 0 <--
MT L1_GETS 0 <--
MT L1_GETX 0 <--
MT L1_PUTX 328
MT L1_PUTX_old 0 <--
MT L2_Replacement 0 <--
MT L2_Replacement_clean 531
MT MEM_Inv 0 <--
M_I L1_GET_INSTR 0 <--
M_I L1_GETS 12
M_I L1_GETX 1
M_I L1_UPGRADE 0 <--
M_I L1_PUTX 0 <--
M_I L1_PUTX_old 107
M_I Mem_Ack 831
M_I MEM_Inv 0 <--
MT_I L1_GET_INSTR 0 <--
MT_I L1_GETS 0 <--
MT_I L1_GETX 0 <--
MT_I L1_UPGRADE 0 <--
MT_I L1_PUTX 0 <--
MT_I L1_PUTX_old 0 <--
MT_I WB_Data 0 <--
MT_I WB_Data_clean 0 <--
MT_I Ack_all 0 <--
MT_I MEM_Inv 0 <--
MCT_I L1_GET_INSTR 0 <--
MCT_I L1_GETS 0 <--
MCT_I L1_GETX 0 <--
MCT_I L1_UPGRADE 0 <--
MCT_I L1_PUTX 0 <--
MCT_I L1_PUTX_old 135
MCT_I WB_Data 485
MCT_I WB_Data_clean 42
MCT_I Ack_all 4
I_I L1_GET_INSTR 0 <--
I_I L1_GETS 0 <--
I_I L1_GETX 0 <--
I_I L1_UPGRADE 0 <--
I_I L1_PUTX 0 <--
I_I L1_PUTX_old 0 <--
I_I Ack 0 <--
I_I Ack_all 0 <--
S_I L1_GET_INSTR 0 <--
S_I L1_GETS 0 <--
S_I L1_GETX 0 <--
S_I L1_UPGRADE 0 <--
S_I L1_PUTX 0 <--
S_I L1_PUTX_old 0 <--
S_I Ack 0 <--
S_I Ack_all 0 <--
S_I MEM_Inv 0 <--
ISS L1_GET_INSTR 0 <--
ISS L1_GETS 0 <--
ISS L1_GETX 0 <--
ISS L1_PUTX 0 <--
ISS L1_PUTX_old 0 <--
ISS L2_Replacement 0 <--
ISS L2_Replacement_clean 708
ISS Mem_Data 89
ISS MEM_Inv 0 <--
IS L1_GET_INSTR 0 <--
IS L1_GETS 0 <--
IS L1_GETX 0 <--
IS L1_PUTX 0 <--
IS L1_PUTX_old 0 <--
IS L2_Replacement 0 <--
IS L2_Replacement_clean 0 <--
IS Mem_Data 0 <--
IS MEM_Inv 0 <--
IM L1_GET_INSTR 0 <--
IM L1_GETS 0 <--
IM L1_GETX 0 <--
IM L1_PUTX 0 <--
IM L1_PUTX_old 0 <--
IM L2_Replacement 0 <--
IM L2_Replacement_clean 4762
IM Mem_Data 746
IM MEM_Inv 0 <--
SS_MB L1_GET_INSTR 0 <--
SS_MB L1_GETS 0 <--
SS_MB L1_GETX 0 <--
SS_MB L1_UPGRADE 0 <--
SS_MB L1_PUTX 0 <--
SS_MB L1_PUTX_old 0 <--
SS_MB L2_Replacement 0 <--
SS_MB L2_Replacement_clean 0 <--
SS_MB Unblock_Cancel 0 <--
SS_MB Exclusive_Unblock 0 <--
SS_MB MEM_Inv 0 <--
MT_MB L1_GET_INSTR 0 <--
MT_MB L1_GETS 0 <--
MT_MB L1_GETX 0 <--
MT_MB L1_UPGRADE 0 <--
MT_MB L1_PUTX 185
MT_MB L1_PUTX_old 138
MT_MB L2_Replacement 0 <--
MT_MB L2_Replacement_clean 7039
MT_MB Unblock_Cancel 0 <--
MT_MB Exclusive_Unblock 860
MT_MB MEM_Inv 0 <--
M_MB L1_GET_INSTR 0 <--
M_MB L1_GETS 0 <--
M_MB L1_GETX 0 <--
M_MB L1_UPGRADE 0 <--
M_MB L1_PUTX 0 <--
M_MB L1_PUTX_old 0 <--
M_MB L2_Replacement 0 <--
M_MB L2_Replacement_clean 0 <--
M_MB Exclusive_Unblock 0 <--
M_MB MEM_Inv 0 <--
MT_IIB L1_GET_INSTR 0 <--
MT_IIB L1_GETS 0 <--
MT_IIB L1_GETX 0 <--
MT_IIB L1_UPGRADE 0 <--
MT_IIB L1_PUTX 0 <--
MT_IIB L1_PUTX_old 0 <--
MT_IIB L2_Replacement 0 <--
MT_IIB L2_Replacement_clean 0 <--
MT_IIB WB_Data 0 <--
MT_IIB WB_Data_clean 0 <--
MT_IIB Unblock 0 <--
MT_IIB MEM_Inv 0 <--
MT_IB L1_GET_INSTR 0 <--
MT_IB L1_GETS 0 <--
MT_IB L1_GETX 0 <--
MT_IB L1_UPGRADE 0 <--
MT_IB L1_PUTX 0 <--
MT_IB L1_PUTX_old 0 <--
MT_IB L2_Replacement 0 <--
MT_IB L2_Replacement_clean 0 <--
MT_IB WB_Data 0 <--
MT_IB WB_Data_clean 0 <--
MT_IB Unblock_Cancel 0 <--
MT_IB MEM_Inv 0 <--
MT_SB L1_GET_INSTR 0 <--
MT_SB L1_GETS 0 <--
MT_SB L1_GETX 0 <--
MT_SB L1_UPGRADE 0 <--
MT_SB L1_PUTX 0 <--
MT_SB L1_PUTX_old 0 <--
MT_SB L2_Replacement 0 <--
MT_SB L2_Replacement_clean 0 <--
MT_SB Unblock 0 <--
MT_SB MEM_Inv 0 <--
Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
memory_total_requests: 1579
memory_reads: 835
memory_writes: 744
memory_refreshes: 744
memory_total_request_delays: 998
memory_delays_per_request: 0.632046
memory_delays_in_input_queue: 152
memory_delays_behind_head_of_bank_queue: 0
memory_delays_stalled_at_head_of_bank_queue: 846
memory_stalls_for_bank_busy: 106
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 69
memory_stalls_for_bus: 344
memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 255
memory_stalls_for_read_read_turnaround: 72
accesses_per_bank: 40 45 45 84 59 65 66 49 45 40 57 49 59 54 41 43 42 38 40 46 45 41 27 34 60 52 50 44 60 42 64 53
--- Directory 0 ---
- Event Counts -
Fetch 835
Data 744
Memory_Data 835
Memory_Ack 744
DMA_READ 0
DMA_WRITE 0
CleanReplacement 87
- Transitions -
I Fetch 835
I DMA_READ 0 <--
I DMA_WRITE 0 <--
ID Fetch 0 <--
ID Data 0 <--
ID Memory_Data 0 <--
ID DMA_READ 0 <--
ID DMA_WRITE 0 <--
ID_W Fetch 0 <--
ID_W Data 0 <--
ID_W Memory_Ack 0 <--
ID_W DMA_READ 0 <--
ID_W DMA_WRITE 0 <--
M Data 744
M DMA_READ 0 <--
M DMA_WRITE 0 <--
M CleanReplacement 87
IM Fetch 0 <--
IM Data 0 <--
IM Memory_Data 835
IM DMA_READ 0 <--
IM DMA_WRITE 0 <--
MI Fetch 0 <--
MI Data 0 <--
MI Memory_Ack 744
MI DMA_READ 0 <--
MI DMA_WRITE 0 <--
M_DRD Data 0 <--
M_DRD DMA_READ 0 <--
M_DRD DMA_WRITE 0 <--
M_DRDI Fetch 0 <--
M_DRDI Data 0 <--
M_DRDI Memory_Ack 0 <--
M_DRDI DMA_READ 0 <--
M_DRDI DMA_WRITE 0 <--
M_DWR Data 0 <--
M_DWR DMA_READ 0 <--
M_DWR DMA_WRITE 0 <--
M_DWRI Fetch 0 <--
M_DWRI Data 0 <--
M_DWRI Memory_Ack 0 <--
M_DWRI DMA_READ 0 <--
M_DWRI DMA_WRITE 0 <--
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