89ea323250
Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
90 lines
1.5 KiB
INI
90 lines
1.5 KiB
INI
[root]
|
|
type=Root
|
|
children=system
|
|
dummy=0
|
|
|
|
[system]
|
|
type=System
|
|
children=cpu membus physmem
|
|
mem_mode=atomic
|
|
physmem=system.physmem
|
|
|
|
[system.cpu]
|
|
type=AtomicSimpleCPU
|
|
children=dtb itb tracer workload
|
|
checker=Null
|
|
clock=500
|
|
cpu_id=0
|
|
defer_registration=false
|
|
do_checkpoint_insts=true
|
|
do_statistics_insts=true
|
|
dtb=system.cpu.dtb
|
|
function_trace=false
|
|
function_trace_start=0
|
|
itb=system.cpu.itb
|
|
max_insts_all_threads=0
|
|
max_insts_any_thread=0
|
|
max_loads_all_threads=0
|
|
max_loads_any_thread=0
|
|
numThreads=1
|
|
phase=0
|
|
progress_interval=0
|
|
simulate_data_stalls=false
|
|
simulate_inst_stalls=false
|
|
system=system
|
|
tracer=system.cpu.tracer
|
|
width=1
|
|
workload=system.cpu.workload
|
|
dcache_port=system.membus.port[2]
|
|
icache_port=system.membus.port[1]
|
|
|
|
[system.cpu.dtb]
|
|
type=AlphaDTB
|
|
size=64
|
|
|
|
[system.cpu.itb]
|
|
type=AlphaITB
|
|
size=48
|
|
|
|
[system.cpu.tracer]
|
|
type=ExeTracer
|
|
|
|
[system.cpu.workload]
|
|
type=LiveProcess
|
|
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
|
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
|
|
egid=100
|
|
env=
|
|
errout=cerr
|
|
euid=100
|
|
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
|
gid=100
|
|
input=cin
|
|
max_stack_size=67108864
|
|
output=cout
|
|
pid=100
|
|
ppid=99
|
|
simpoint=0
|
|
system=system
|
|
uid=100
|
|
|
|
[system.membus]
|
|
type=Bus
|
|
block_size=64
|
|
bus_id=0
|
|
clock=1000
|
|
header_cycles=1
|
|
responder_set=false
|
|
width=64
|
|
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
|
|
|
[system.physmem]
|
|
type=PhysicalMemory
|
|
file=
|
|
latency=30000
|
|
latency_var=0
|
|
null=false
|
|
range=0:134217727
|
|
zero=false
|
|
port=system.membus.port[0]
|
|
|