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gem5/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
Steve Reinhardt 89ea323250 Update stats for new prefetching fixes. 
Prefetching is not enabled in any of our regressions, so no significant
stat values have changed, but zero-valued prefetch stats no longer
show up when prefetching is disabled so there are noticable changes
in the reference stat files anyway.
2009-02-16 12:09:45 -05:00

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---------- Begin Simulation Statistics ----------
host_inst_rate 1969135 # Simulator instruction rate (inst/s)
host_mem_usage 203124 # Number of bytes of host memory used
host_seconds 305.65 # Real time elapsed on the host
host_tick_rate 2545444210 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.778004 # Number of seconds simulated
sim_ticks 778003833000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 21095.452016 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18095.452016 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4245080000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 3641384000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 55999.984797 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.984797 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 39122430 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 18417891000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.008337 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 328891 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 17431218000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 42750.401322 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency
system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 22662971000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.003443 # miss rate for demand accesses
system.cpu.dcache.demand_misses 530123 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 21072602000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 42750.401322 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 153435240 # number of overall hits
system.cpu.dcache.overall_miss_latency 22662971000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses
system.cpu.dcache.overall_misses 530123 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 21072602000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4094.195523 # Cycle average of tags in use
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 579204000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 325723 # number of writebacks
system.cpu.dtb.accesses 153970296 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 153965363 # DTB hits
system.cpu.dtb.misses 4933 # DTB misses
system.cpu.dtb.read_accesses 114516673 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 114514042 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.write_accesses 39453623 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 39451321 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 44520000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 44520000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_misses 795 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 42135000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 601861103 # number of overall hits
system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_misses 795 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 42135000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 673.225223 # Cycle average of tags in use
system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 601861918 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 601861898 # ITB hits
system.cpu.itb.misses 20 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 13216476000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 254163 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 10166520000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 254163 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 167236 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1809132000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.172210 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 34791 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1391640000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.172210 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 34791 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51996.520715 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 3885596000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2989120000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 3.519863 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 167236 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 15025608000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.633407 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 288954 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 11558160000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.633407 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 288954 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 167236 # number of overall hits
system.cpu.l2cache.overall_miss_latency 15025608000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 288954 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 11558160000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.633407 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 288954 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 84513 # number of replacements
system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 16343.542372 # Cycle average of tags in use
system.cpu.l2cache.total_refs 352458 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 63194 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1556007666 # number of cpu cycles simulated
system.cpu.num_insts 601856964 # Number of instructions executed
system.cpu.num_refs 154866966 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
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