Andreas Hansson a8480fe1c3 config: Move the memory instantiation outside FSConfig ... This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers.		2013-08-19 03:52:27 -04:00
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Benchmarks.py	configs: add run scripts for ics/gb versions of android and bbench	2012-06-11 11:07:42 -04:00
CacheConfig.py	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
Caches.py	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
cpu2000.py	cpu2000: Add missing art benchmark to all	2012-01-09 18:08:20 -06:00
CpuConfig.py	config: Cleanup CPU configuration	2013-02-15 17:40:08 -05:00
FSConfig.py	config: Move the memory instantiation outside FSConfig	2013-08-19 03:52:27 -04:00
MemConfig.py	mem: More descriptive DRAM config names	2013-05-30 12:54:14 -04:00
O3_ARM_v7a.py	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
Options.py	Configs: Fix up maxtick and maxtime	2013-07-18 14:46:54 -05:00
Simulation.py	Configs: Fix up maxtick and maxtime	2013-07-18 14:46:54 -05:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00