gem5/src/cpu/minor
Mitch Hayenga a5c4eb3de9 isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
2015-09-30 11:14:19 -05:00
..
activity.cc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
activity.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
buffers.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
cpu.cc cpu: Fix Minor drain issues when switched out 2015-07-31 17:04:59 +01:00
cpu.hh sim: Refactor and simplify the drain API 2015-07-07 09:51:05 +01:00
decode.cc arm: Fixes based on UBSan and static analysis 2014-11-14 03:53:51 -05:00
decode.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
dyn_inst.cc revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
dyn_inst.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
exec_context.hh cpu: Add per-thread monitors 2015-09-30 11:14:19 -05:00
execute.cc isa,cpu: Add support for FS SMT Interrupts 2015-09-30 11:14:19 -05:00
execute.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
fetch1.cc cpu: Add per-thread monitors 2015-09-30 11:14:19 -05:00
fetch1.hh mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
fetch2.cc arm: Fixes based on UBSan and static analysis 2014-11-14 03:53:51 -05:00
fetch2.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
func_unit.cc arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
func_unit.hh arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
lsq.cc cpu: Add per-thread monitors 2015-09-30 11:14:19 -05:00
lsq.hh mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
MinorCPU.py cpu: re-organizes the branch predictor structure. 2015-04-13 17:33:57 -05:00
pipe_data.cc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
pipe_data.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
pipeline.cc sim: Refactor and simplify the drain API 2015-07-07 09:51:05 +01:00
pipeline.hh sim: Refactor and simplify the drain API 2015-07-07 09:51:05 +01:00
SConscript cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
SConsopts arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
scoreboard.cc revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
scoreboard.hh revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
stats.cc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
stats.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
trace.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00