143 lines
4.9 KiB
C++
143 lines
4.9 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#ifndef __MEM_TPORT_HH__
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#define __MEM_TPORT_HH__
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/**
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* @file
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*
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* Declaration of SimpleTimingPort.
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*/
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#include "mem/port.hh"
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#include "sim/eventq.hh"
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#include <list>
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#include <string>
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/**
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* A simple port for interfacing objects that basically have only
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* functional memory behavior (e.g. I/O devices) to the memory system.
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* Both timing and functional accesses are implemented in terms of
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* atomic accesses. A derived port class thus only needs to provide
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* recvAtomic() to support all memory access modes.
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*
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* The tricky part is handling recvTiming(), where the response must
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* be scheduled separately via a later call to sendTiming(). This
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* feature is handled by scheduling an internal event that calls
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* sendTiming() after a delay, and optionally rescheduling the
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* response if it is nacked.
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*/
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class SimpleTimingPort : public Port
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{
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protected:
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/** A list of outgoing timing response packets that haven't been
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* serviced yet. */
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std::list<PacketPtr> transmitList;
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/**
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* This class is used to implemented sendTiming() with a delay. When
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* a delay is requested a new event is created. When the event time
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* expires it attempts to send the packet. If it cannot, the packet
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* is pushed onto the transmit list to be sent when recvRetry() is
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* called. */
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class SendEvent : public Event
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{
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SimpleTimingPort *port;
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PacketPtr packet;
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public:
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SendEvent(SimpleTimingPort *p, PacketPtr pkt, Tick t)
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: Event(&mainEventQueue), port(p), packet(pkt)
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{ setFlags(AutoDelete); schedule(curTick + t); }
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virtual void process();
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virtual const char *description()
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{ return "Future scheduled sendTiming event"; }
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};
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/** Number of timing requests that are emulating the device timing before
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* attempting to end up on the bus.
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*/
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int outTiming;
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/** If we need to drain, keep the drain event around until we're done
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* here.*/
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Event *drainEvent;
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/** Schedule a sendTiming() event to be called in the future. */
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void sendTimingLater(PacketPtr pkt, Tick time)
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{ outTiming++; new SendEvent(this, pkt, time); }
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/** This function is notification that the device should attempt to send a
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* packet again. */
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virtual void recvRetry();
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/** Implemented using recvAtomic(). */
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void recvFunctional(PacketPtr pkt);
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/** Implemented using recvAtomic(). */
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bool recvTiming(PacketPtr pkt);
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/**
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* Simple ports generally don't care about any status
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* changes... can always override this in cases where that's not
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* true. */
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virtual void recvStatusChange(Status status) { }
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public:
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SimpleTimingPort(std::string pname)
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: Port(pname), outTiming(0), drainEvent(NULL)
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{}
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/** Hook for draining timing accesses from the system. The
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* associated SimObject's drain() functions should be implemented
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* something like this when this class is used:
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\code
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PioDevice::drain(Event *de)
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{
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unsigned int count;
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count = SimpleTimingPort->drain(de);
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if (count)
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changeState(Draining);
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else
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changeState(Drained);
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return count;
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}
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\endcode
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*/
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unsigned int drain(Event *de);
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};
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#endif // __MEM_TPORT_HH__
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