5c79eb0410
arch/sparc/isa/base.isa:
arch/sparc/isa/decoder.isa:
arch/sparc/isa/formats.isa:
arch/sparc/isa/formats/branch.isa:
arch/sparc/isa/formats/integerop.isa:
arch/sparc/isa/formats/mem.isa:
arch/sparc/isa/formats/nop.isa:
arch/sparc/isa/formats/trap.isa:
arch/sparc/isa/formats/unknown.isa:
arch/sparc/isa/includes.isa:
arch/sparc/isa/operands.isa:
Fixes towards running in syscall emulation mode.
arch/sparc/linux/process.cc:
Fixed the assert and comment to check that the Num_Syscall_Descs is less than or equal to 284. Why does this assert need to exist anyway?
base/loader/elf_object.cc:
Cleared out comments about resolved issues.
cpu/simple/cpu.cc:
Use NNPC for both SPARC and MIPS, instead of just MIPS
configs/test/hello_sparc:
A test program for SPARC which prints "Hello World!"
--HG--
rename : arch/sparc/isa/formats/noop.isa => arch/sparc/isa/formats/nop.isa
extra : convert_revision : 10b3e3b9f21c215d809cffa930448007102ba698
129 lines
3.7 KiB
Text
129 lines
3.7 KiB
Text
////////////////////////////////////////////////////////////////////
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//
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// Mem instructions
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//
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output header {{
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/**
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* Base class for memory operations.
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*/
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class Mem : public SparcStaticInst
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{
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protected:
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// Constructor
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Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
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SparcStaticInst(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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};
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/**
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* Class for memory operations which use an immediate offset.
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*/
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class MemImm : public Mem
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{
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protected:
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// Constructor
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MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
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Mem(mnem, _machInst, __opClass), imm(SIMM13)
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{
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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int imm;
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};
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}};
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output decoder {{
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std::string Mem::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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bool load = (_numDestRegs == 1);
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printMnemonic(response, mnemonic);
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if(!load)
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{
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printReg(response, _srcRegIdx[0]);
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ccprintf(response, ", ");
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}
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ccprintf(response, "[ ");
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printReg(response, _srcRegIdx[load ? 0 : 1]);
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ccprintf(response, " + ");
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printReg(response, _srcRegIdx[load ? 1 : 2]);
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ccprintf(response, " ]");
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if(load)
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{
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ccprintf(response, ", ");
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printReg(response, _destRegIdx[0]);
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}
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return response.str();
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}
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std::string MemImm::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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bool load = (_numDestRegs == 1);
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printMnemonic(response, mnemonic);
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if(!load)
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{
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printReg(response, _srcRegIdx[0]);
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ccprintf(response, ", ");
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}
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ccprintf(response, "[ ");
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printReg(response, _srcRegIdx[load ? 0 : 1]);
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ccprintf(response, " + 0x%x ]", imm);
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if(load)
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{
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ccprintf(response, ", ");
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printReg(response, _destRegIdx[0]);
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}
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return response.str();
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}
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}};
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def template MemExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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%(code)s;
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if(fault == NoFault)
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{
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//Write the resulting state to the execution context
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%(op_wb)s;
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}
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return fault;
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}
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}};
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// Primary format for memory instructions:
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def format Mem(code, *opt_flags) {{
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addrCalcReg = 'EA = Rs1 + Rs2;'
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addrCalcImm = 'EA = Rs1 + SIMM13;'
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iop = genCompositeIop(code, name, Name, 'Mem',
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opt_flags, ea_code=addrCalcReg)
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iop_imm = genCompositeIop(code, name, Name + 'Imm', 'MemImm',
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opt_flags, ea_code=addrCalcImm)
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header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm)
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decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
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decode_block = ROrImmDecode.subst(iop)
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exec_output = MemExecute.subst(iop) + MemExecute.subst(iop_imm)
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}};
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