gem5/cpu/intr_control.cc
Kevin Lim 11aead894d Updates for the quiesceEvent that was added to the XC.
Also several files need to include system.hh or symtab.hh.  This is because exec_context.hh has less #includes than before, requiring some of the files that include it to include some other files as well.

arch/alpha/faults.cc:
    Avoid accessing XC directly.
arch/alpha/stacktrace.cc:
    StackTrace needs to include system.hh.
cpu/cpu_exec_context.cc:
    Update for change to CPUExecContext.
cpu/cpu_exec_context.hh:
    Make quiesce events use CPUExecContext instead of ExecContext.  Include functions to allow the quiesce event and last activate/suspend be accessed.
cpu/exec_context.hh:
    Include functions for quiesceEvent.
cpu/intr_control.cc:
    Needs to include cpu/exec_context.hh.
cpu/profile.cc:
    Needs to include symtab.hh for the symbol table.
cpu/profile.hh:
    Needs forward declare of ExecContext.
cpu/simple/cpu.cc:
    Rename xc to cpuXC.
dev/tsunami_cchip.cc:
    Needs to include exec_context.hh.
kern/kernel_stats.cc:
    Needs to include system.hh.
kern/linux/events.cc:
    Needs to include system.hh.

    Also avoid accessing objects directly from the XC.
kern/tru64/dump_mbuf.cc:
    Include symtab.hh for the SymbolTable and system.hh.
kern/tru64/tru64_events.cc:
    Include system.hh
sim/pseudo_inst.cc:
    Avoid accessing objects directly within the XC.

--HG--
extra : convert_revision : 78fe30d98cd20f7403fa216f772071458b675c84
2006-03-07 19:59:12 -05:00

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3.1 KiB
C++

/*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <string>
#include <vector>
#include "cpu/base.hh"
#include "cpu/exec_context.hh"
#include "cpu/intr_control.hh"
#include "sim/builder.hh"
#include "sim/sim_object.hh"
using namespace std;
IntrControl::IntrControl(const string &name, BaseCPU *c)
: SimObject(name), cpu(c)
{}
/* @todo
*Fix the cpu sim object parameter to be a system pointer
*instead, to avoid some extra dereferencing
*/
void
IntrControl::post(int int_num, int index)
{
std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
BaseCPU *temp = xcvec[0]->getCpuPtr();
temp->post_interrupt(int_num, index);
}
void
IntrControl::post(int cpu_id, int int_num, int index)
{
std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
BaseCPU *temp = xcvec[cpu_id]->getCpuPtr();
temp->post_interrupt(int_num, index);
}
void
IntrControl::clear(int int_num, int index)
{
std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
BaseCPU *temp = xcvec[0]->getCpuPtr();
temp->clear_interrupt(int_num, index);
}
void
IntrControl::clear(int cpu_id, int int_num, int index)
{
std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
BaseCPU *temp = xcvec[cpu_id]->getCpuPtr();
temp->clear_interrupt(int_num, index);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
SimObjectParam<BaseCPU *> cpu;
END_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
BEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl)
INIT_PARAM(cpu, "the cpu")
END_INIT_SIM_OBJECT_PARAMS(IntrControl)
CREATE_SIM_OBJECT(IntrControl)
{
return new IntrControl(getInstanceName(), cpu);
}
REGISTER_SIM_OBJECT("IntrControl", IntrControl)