1990 lines
227 KiB
Text
1990 lines
227 KiB
Text
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 1.843590 # Number of seconds simulated
|
|
sim_ticks 1843589966000 # Number of ticks simulated
|
|
final_tick 1843589966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 235004 # Simulator instruction rate (inst/s)
|
|
host_op_rate 235004 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 6029262323 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 334496 # Number of bytes of host memory used
|
|
host_seconds 305.77 # Real time elapsed on the host
|
|
sim_insts 71858166 # Number of instructions simulated
|
|
sim_ops 71858166 # Number of ops (including micro ops) simulated
|
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
system.clk_domain.clock 1000 # Clock period in ticks
|
|
system.physmem.bytes_read::cpu0.inst 498752 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.data 20812864 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.inst 142016 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.data 1542464 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu2.inst 270784 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu2.data 2513408 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 25781248 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu0.inst 498752 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu1.inst 142016 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu2.inst 270784 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 911552 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_written::writebacks 7470272 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::total 7470272 # Number of bytes written to this memory
|
|
system.physmem.num_reads::cpu0.inst 7793 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.data 325201 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.inst 2219 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.data 24101 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu2.inst 4231 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu2.data 39272 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 402832 # Number of read requests responded to by this memory
|
|
system.physmem.num_writes::writebacks 116723 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::total 116723 # Number of write requests responded to by this memory
|
|
system.physmem.bw_read::cpu0.inst 270533 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.data 11289313 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.inst 77032 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.data 836663 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu2.inst 146879 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu2.data 1363323 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 13984264 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu0.inst 270533 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu1.inst 77032 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu2.inst 146879 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 494444 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::writebacks 4052025 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::total 4052025 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::writebacks 4052025 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.inst 270533 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.data 11289313 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.inst 77032 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.data 836663 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu2.inst 146879 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu2.data 1363323 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 18036288 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.readReqs 69838 # Number of read requests accepted
|
|
system.physmem.writeReqs 43200 # Number of write requests accepted
|
|
system.physmem.readBursts 69838 # Number of DRAM read bursts, including those serviced by the write queue
|
|
system.physmem.writeBursts 43200 # Number of DRAM write bursts, including those merged in the write queue
|
|
system.physmem.bytesReadDRAM 4468672 # Total number of bytes read from DRAM
|
|
system.physmem.bytesReadWrQ 960 # Total number of bytes read from write queue
|
|
system.physmem.bytesWritten 2763328 # Total number of bytes written to DRAM
|
|
system.physmem.bytesReadSys 4469632 # Total read bytes from the system interface side
|
|
system.physmem.bytesWrittenSys 2764800 # Total written bytes from the system interface side
|
|
system.physmem.servicedByWrQ 15 # Number of DRAM read bursts serviced by the write queue
|
|
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
|
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
|
system.physmem.perBankRdBursts::0 4348 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::1 4129 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::2 4337 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::3 4598 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::4 3888 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::5 4661 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::6 4235 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::7 4148 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::8 4712 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::9 4417 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::10 4595 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::11 4084 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::12 4058 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::13 4570 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::14 4705 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::15 4338 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::0 2799 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::1 2436 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::2 2792 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::3 3104 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::4 2401 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::5 2782 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::6 2480 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::7 2289 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::8 3134 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::9 2510 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::10 2861 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::11 2441 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::12 2439 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::13 2831 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::14 3033 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::15 2845 # Per bank write bursts
|
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
|
system.physmem.numWrRetry 4 # Number of times write queue was full causing retry
|
|
system.physmem.totGap 1842577981000 # Total gap between requests
|
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::6 69838 # Read request sizes (log2)
|
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::6 43200 # Write request sizes (log2)
|
|
system.physmem.rdQLenPdf::0 49697 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::1 8415 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::2 6353 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::3 5333 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::1 53 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::2 50 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 45 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 57 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 42 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 50 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 43 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 45 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 38 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 37 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 746 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 1290 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 2252 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 1827 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 2332 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 2138 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 2031 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 2229 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 2470 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 2287 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 3139 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 3240 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 2716 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 2830 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 2718 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 2654 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 2141 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::32 1916 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::33 85 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::34 60 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::36 69 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 41 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 70 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::39 42 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 34 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 45 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 53 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 62 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 73 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 51 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 84 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 96 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 64 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 50 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 33 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 31 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 24 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see
|
|
system.physmem.bytesPerActivate::samples 20081 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::mean 360.141427 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::gmean 203.044984 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::stdev 371.054922 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::0-127 7137 35.54% 35.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-255 4621 23.01% 58.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-383 1666 8.30% 66.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 928 4.62% 71.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 708 3.53% 75.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 489 2.44% 77.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 446 2.22% 79.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 393 1.96% 81.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 3693 18.39% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 20081 # Bytes accessed per row activation
|
|
system.physmem.rdPerTurnAround::samples 1852 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::mean 37.694924 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::stdev 845.707136 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::0-2047 1850 99.89% 99.89% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::34816-36863 1 0.05% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 1852 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 1852 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 23.313715 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 18.866365 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 22.527044 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::0-7 41 2.21% 2.21% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::8-15 7 0.38% 2.59% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-23 1554 83.91% 86.50% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-31 22 1.19% 87.69% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-39 8 0.43% 88.12% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-47 17 0.92% 89.04% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-55 85 4.59% 93.63% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-63 1 0.05% 93.68% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-71 5 0.27% 93.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-79 12 0.65% 94.60% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-87 79 4.27% 98.87% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-95 1 0.05% 98.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-103 1 0.05% 98.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::104-111 2 0.11% 99.08% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::120-127 2 0.11% 99.19% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-135 1 0.05% 99.24% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-167 2 0.11% 99.35% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::168-175 1 0.05% 99.41% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-183 4 0.22% 99.62% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::192-199 2 0.11% 99.73% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::200-207 1 0.05% 99.78% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::208-215 1 0.05% 99.84% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::224-231 1 0.05% 99.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::240-247 1 0.05% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::256-263 1 0.05% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 1852 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 868841000 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 2178022250 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 349115000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 12443.48 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 31193.48 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 2.42 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 1.50 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 2.42 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 1.50 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.03 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 4.02 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 58950 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 33969 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 84.43 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 78.63 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 16300518.24 # Average gap between requests
|
|
system.physmem.pageHitRate 82.21 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 75327840 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 41027250 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 267883200 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 136617840 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 89190744240 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 36136650240 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 799618982250 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 925467232860 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 667.951944 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 1310356278000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 45598540000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 9770912000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 76484520 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 41621250 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 276736200 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 143169120 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 89190744240 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 35633622105 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 799038075000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 924400452435 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 668.003354 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 1311078051250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 45598540000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 9034735750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu0.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu0.dtb.read_hits 4864866 # DTB read hits
|
|
system.cpu0.dtb.read_misses 6190 # DTB read misses
|
|
system.cpu0.dtb.read_acv 126 # DTB read access violations
|
|
system.cpu0.dtb.read_accesses 429298 # DTB read accesses
|
|
system.cpu0.dtb.write_hits 3435008 # DTB write hits
|
|
system.cpu0.dtb.write_misses 688 # DTB write misses
|
|
system.cpu0.dtb.write_acv 84 # DTB write access violations
|
|
system.cpu0.dtb.write_accesses 165213 # DTB write accesses
|
|
system.cpu0.dtb.data_hits 8299874 # DTB hits
|
|
system.cpu0.dtb.data_misses 6878 # DTB misses
|
|
system.cpu0.dtb.data_acv 210 # DTB access violations
|
|
system.cpu0.dtb.data_accesses 594511 # DTB accesses
|
|
system.cpu0.itb.fetch_hits 2740787 # ITB hits
|
|
system.cpu0.itb.fetch_misses 3088 # ITB misses
|
|
system.cpu0.itb.fetch_acv 104 # ITB acv
|
|
system.cpu0.itb.fetch_accesses 2743875 # ITB accesses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.read_acv 0 # DTB read access violations
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.write_acv 0 # DTB write access violations
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.data_hits 0 # DTB hits
|
|
system.cpu0.itb.data_misses 0 # DTB misses
|
|
system.cpu0.itb.data_acv 0 # DTB access violations
|
|
system.cpu0.itb.data_accesses 0 # DTB accesses
|
|
system.cpu0.numCycles 928566651 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 6425 # number of quiesce instructions executed
|
|
system.cpu0.kern.inst.hwrei 211440 # number of hwrei instructions executed
|
|
system.cpu0.kern.ipl_count::0 74803 40.97% 40.97% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::22 1880 1.03% 42.11% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::31 105703 57.89% 100.00% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::total 182589 # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_good::0 73436 49.30% 49.30% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::22 1880 1.26% 50.70% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::31 73436 49.30% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::total 148955 # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_ticks::0 1820420490500 98.74% 98.74% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::21 39420000 0.00% 98.75% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::22 369089000 0.02% 98.77% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::31 22760232500 1.23% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::total 1843589232000 # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::31 0.694739 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::total 0.815794 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
|
system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
|
system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
|
system.cpu0.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
|
system.cpu0.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
|
system.cpu0.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu0.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu0.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu0.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu0.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu0.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu0.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu0.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu0.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu0.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu0.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu0.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu0.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu0.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu0.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu0.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu0.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu0.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu0.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu0.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu0.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu0.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu0.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu0.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu0.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu0.kern.syscall::total 326 # number of syscalls executed
|
|
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed
|
|
system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
|
|
system.cpu0.kern.callpal::swpipl 175328 91.20% 93.41% # number of callpals executed
|
|
system.cpu0.kern.callpal::rdps 6784 3.53% 96.94% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed
|
|
system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed
|
|
system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed
|
|
system.cpu0.kern.callpal::rti 5177 2.69% 99.64% # number of callpals executed
|
|
system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::total 192243 # number of callpals executed
|
|
system.cpu0.kern.mode_switch::kernel 5921 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches
|
|
system.cpu0.kern.mode_good::kernel 1908
|
|
system.cpu0.kern.mode_good::user 1739
|
|
system.cpu0.kern.mode_good::idle 169
|
|
system.cpu0.kern.mode_switch_good::kernel 0.322243 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_ticks::kernel 29995203000 1.63% 1.63% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks::user 2591439000 0.14% 1.77% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks::idle 1811002588000 98.23% 100.00% # number of ticks spent at the given mode
|
|
system.cpu0.kern.swap_context 4175 # number of times the context was actually changed
|
|
system.cpu0.committedInsts 32582067 # Number of instructions committed
|
|
system.cpu0.committedOps 32582067 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 30467910 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 163902 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 798062 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 4326152 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 30467910 # number of integer instructions
|
|
system.cpu0.num_fp_insts 163902 # number of float instructions
|
|
system.cpu0.num_int_register_reads 42599897 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 22343200 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 84869 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 86282 # number of times the floating registers were written
|
|
system.cpu0.num_mem_refs 8329687 # number of memory refs
|
|
system.cpu0.num_load_insts 4886082 # Number of load instructions
|
|
system.cpu0.num_store_insts 3443605 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 904742998.451047 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 23823652.548953 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.025656 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.974344 # Percentage of idle cycles
|
|
system.cpu0.Branches 5381713 # Number of branches fetched
|
|
system.cpu0.op_class::No_OpClass 1604740 4.92% 4.92% # Class of executed instruction
|
|
system.cpu0.op_class::IntAlu 21953705 67.37% 72.29% # Class of executed instruction
|
|
system.cpu0.op_class::IntMult 32143 0.10% 72.39% # Class of executed instruction
|
|
system.cpu0.op_class::IntDiv 0 0.00% 72.39% # Class of executed instruction
|
|
system.cpu0.op_class::FloatAdd 13006 0.04% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCmp 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMult 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::FloatDiv 1630 0.01% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::FloatSqrt 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAdd 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAddAcc 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAlu 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCmp 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCvt 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMisc 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMult 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMultAcc 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdSqrt 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMult 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.43% # Class of executed instruction
|
|
system.cpu0.op_class::MemRead 5016904 15.39% 87.83% # Class of executed instruction
|
|
system.cpu0.op_class::MemWrite 3446714 10.58% 98.40% # Class of executed instruction
|
|
system.cpu0.op_class::IprAccess 520313 1.60% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::total 32589155 # Class of executed instruction
|
|
system.cpu0.dcache.tags.replacements 1393265 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 511.997813 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 13241654 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 1393777 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 9.500554 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.747103 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu1.data 121.216699 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu2.data 136.034010 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497553 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.236751 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.265691 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 63386315 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 63386315 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 4025113 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 1019893 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu2.data 2537393 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 7582399 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 3145683 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 772678 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu2.data 1357185 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 5275546 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114073 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19050 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51175 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 184298 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122917 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21014 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55400 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 199331 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 7170796 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 1792571 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu2.data 3894578 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 12857945 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 7170796 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 1792571 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu2.data 3894578 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 12857945 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 726690 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 86811 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu2.data 548555 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 1362056 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 165054 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 38389 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu2.data 671866 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 875309 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9398 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2090 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7703 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 19191 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 3 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 891744 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 125200 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu2.data 1220421 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 2237365 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 891744 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 125200 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu2.data 1220421 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 2237365 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2310208500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8890735000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 11200943500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2130423000 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 29514538622 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 31644961622 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27861500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 150253000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 178114500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 108000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 108000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 4440631500 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu2.data 38405273622 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 42845905122 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 4440631500 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu2.data 38405273622 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 42845905122 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 4751803 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 1106704 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu2.data 3085948 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 8944455 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3310737 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 811067 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu2.data 2029051 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 6150855 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123471 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21140 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58878 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 203489 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 122918 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21014 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55403 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 199335 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 8062540 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 1917771 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu2.data 5114999 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 15095310 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 8062540 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 1917771 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu2.data 5114999 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 15095310 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.152929 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.078441 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.177759 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.152279 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049854 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.047331 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.331123 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.142307 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076115 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.098865 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130830 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094310 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000054 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000020 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.110603 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.065284 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.238597 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.148216 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.110603 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065284 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.238597 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.148216 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 26611.932820 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16207.554393 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 8223.555786 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 55495.662820 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 43929.204070 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 36152.903286 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13330.861244 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 19505.776970 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9281.147413 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 36000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35468.302716 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31468.873136 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 19150.163305 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35468.302716 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31468.873136 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 19150.163305 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 1652562 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 2580 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 59814 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 12 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.628348 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 215 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 835864 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 835864 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 288309 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 288309 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 572598 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 572598 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1581 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1581 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu2.data 860907 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 860907 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu2.data 860907 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 860907 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 86811 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 260246 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 347057 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 38389 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99268 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 137657 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2090 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6122 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8212 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 125200 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu2.data 359514 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 484714 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 125200 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu2.data 359514 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 484714 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1329 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1323 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2652 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1618 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 1898 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3516 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2947 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3221 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6168 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2223397500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4676165000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6899562500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2092034000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4615486880 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6707520880 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 25771500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 77436500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103208000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 105000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 105000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4315431500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9291651880 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 13607083380 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4315431500 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 9291651880 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 13607083380 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 293417500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 298094000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 591511500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 372517000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 424017500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 796534500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 665934500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 722111500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1388046000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.078441 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084333 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038801 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.047331 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.048923 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022380 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.098865 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103978 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040356 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000015 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065284 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070286 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.032110 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065284 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070286 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.032110 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 25611.932820 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17968.249272 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19880.199794 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54495.662820 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46495.213765 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48726.333423 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12330.861244 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12648.889252 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12567.949342 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 35000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 35000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34468.302716 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25845.034908 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28072.396052 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34468.302716 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25845.034908 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28072.396052 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 220780.662152 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 225316.704460 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223043.552036 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 230233.003708 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 223402.265543 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 226545.648464 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 225970.308789 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 224188.606023 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225039.883268 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 963447 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.175727 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 41538422 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 963958 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 43.091527 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 10558559500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 261.250530 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu1.inst 81.956033 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu2.inst 167.969164 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.510255 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.160070 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.328065 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.998390 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 43483376 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 43483376 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 32077016 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 7032806 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu2.inst 2428600 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 41538422 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 32077016 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 7032806 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu2.inst 2428600 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 41538422 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 32077016 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 7032806 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu2.inst 2428600 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 41538422 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 512139 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 125213 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu2.inst 343464 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 980816 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 512139 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 125213 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu2.inst 343464 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 980816 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 512139 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 125213 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu2.inst 343464 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 980816 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1899535500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5061406468 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 6960941968 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 1899535500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu2.inst 5061406468 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 6960941968 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 1899535500 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu2.inst 5061406468 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 6960941968 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 32589155 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 7158019 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu2.inst 2772064 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 42519238 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 32589155 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 7158019 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu2.inst 2772064 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 42519238 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 32589155 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 7158019 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu2.inst 2772064 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 42519238 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015715 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.017493 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.123902 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.023068 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015715 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.017493 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.123902 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.023068 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015715 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.017493 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.123902 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.023068 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 15170.433581 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14736.352188 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 7097.092592 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 15170.433581 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14736.352188 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 7097.092592 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 15170.433581 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14736.352188 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 7097.092592 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 8655 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 361 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.975069 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.writebacks::writebacks 963447 # number of writebacks
|
|
system.cpu0.icache.writebacks::total 963447 # number of writebacks
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16678 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 16678 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu2.inst 16678 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 16678 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu2.inst 16678 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 16678 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 125213 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 326786 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 451999 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 125213 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu2.inst 326786 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 451999 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 125213 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu2.inst 326786 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 451999 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1774322500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4489110472 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 6263432972 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1774322500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4489110472 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 6263432972 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1774322500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4489110472 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 6263432972 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.017493 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.117885 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010630 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.017493 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.117885 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.010630 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.017493 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.117885 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.010630 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14170.433581 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13737.156647 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13857.183250 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14170.433581 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13737.156647 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13857.183250 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14170.433581 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13737.156647 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13857.183250 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu1.dtb.read_hits 1125881 # DTB read hits
|
|
system.cpu1.dtb.read_misses 1262 # DTB read misses
|
|
system.cpu1.dtb.read_acv 31 # DTB read access violations
|
|
system.cpu1.dtb.read_accesses 118172 # DTB read accesses
|
|
system.cpu1.dtb.write_hits 832506 # DTB write hits
|
|
system.cpu1.dtb.write_misses 154 # DTB write misses
|
|
system.cpu1.dtb.write_acv 18 # DTB write access violations
|
|
system.cpu1.dtb.write_accesses 48626 # DTB write accesses
|
|
system.cpu1.dtb.data_hits 1958387 # DTB hits
|
|
system.cpu1.dtb.data_misses 1416 # DTB misses
|
|
system.cpu1.dtb.data_acv 49 # DTB access violations
|
|
system.cpu1.dtb.data_accesses 166798 # DTB accesses
|
|
system.cpu1.itb.fetch_hits 755228 # ITB hits
|
|
system.cpu1.itb.fetch_misses 636 # ITB misses
|
|
system.cpu1.itb.fetch_acv 28 # ITB acv
|
|
system.cpu1.itb.fetch_accesses 755864 # ITB accesses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.read_acv 0 # DTB read access violations
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.write_acv 0 # DTB write access violations
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.data_hits 0 # DTB hits
|
|
system.cpu1.itb.data_misses 0 # DTB misses
|
|
system.cpu1.itb.data_acv 0 # DTB access violations
|
|
system.cpu1.itb.data_accesses 0 # DTB accesses
|
|
system.cpu1.numCycles 953452805 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
|
|
system.cpu1.kern.mode_switch::kernel 0 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::user 0 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::idle 0 # number of protection mode switches
|
|
system.cpu1.kern.mode_good::kernel 0
|
|
system.cpu1.kern.mode_good::user 0
|
|
system.cpu1.kern.mode_good::idle 0
|
|
system.cpu1.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::user nan # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::total nan # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
|
|
system.cpu1.kern.swap_context 0 # number of times the context was actually changed
|
|
system.cpu1.committedInsts 7156553 # Number of instructions committed
|
|
system.cpu1.committedOps 7156553 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 6641394 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 39637 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 205363 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 849545 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 6641394 # number of integer instructions
|
|
system.cpu1.num_fp_insts 39637 # number of float instructions
|
|
system.cpu1.num_int_register_reads 9238548 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 4861490 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 20633 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 21093 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 1965214 # number of memory refs
|
|
system.cpu1.num_load_insts 1130466 # Number of load instructions
|
|
system.cpu1.num_store_insts 834748 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 924897133.577308 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 28555671.422692 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.029950 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.970050 # Percentage of idle cycles
|
|
system.cpu1.Branches 1119461 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 390354 5.45% 5.45% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 4632011 64.71% 70.16% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 7720 0.11% 70.27% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 3352 0.05% 70.32% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 70.32% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 70.32% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 70.32% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 449 0.01% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.33% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 1159039 16.19% 86.52% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 835953 11.68% 98.20% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 129140 1.80% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 7158018 # Class of executed instruction
|
|
system.cpu2.branchPred.lookups 10791255 # Number of BP lookups
|
|
system.cpu2.branchPred.condPredicted 10058403 # Number of conditional branches predicted
|
|
system.cpu2.branchPred.condIncorrect 121654 # Number of conditional branches incorrect
|
|
system.cpu2.branchPred.BTBLookups 8435844 # Number of BTB lookups
|
|
system.cpu2.branchPred.BTBHits 6655738 # Number of BTB hits
|
|
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu2.branchPred.BTBHitPct 78.898306 # BTB Hit Percentage
|
|
system.cpu2.branchPred.usedRAS 298678 # Number of times the RAS was used to get a target.
|
|
system.cpu2.branchPred.RASInCorrect 7720 # Number of incorrect RAS predictions.
|
|
system.cpu2.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu2.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu2.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu2.dtb.read_hits 3519605 # DTB read hits
|
|
system.cpu2.dtb.read_misses 12192 # DTB read misses
|
|
system.cpu2.dtb.read_acv 125 # DTB read access violations
|
|
system.cpu2.dtb.read_accesses 255658 # DTB read accesses
|
|
system.cpu2.dtb.write_hits 2173211 # DTB write hits
|
|
system.cpu2.dtb.write_misses 2700 # DTB write misses
|
|
system.cpu2.dtb.write_acv 124 # DTB write access violations
|
|
system.cpu2.dtb.write_accesses 93379 # DTB write accesses
|
|
system.cpu2.dtb.data_hits 5692816 # DTB hits
|
|
system.cpu2.dtb.data_misses 14892 # DTB misses
|
|
system.cpu2.dtb.data_acv 249 # DTB access violations
|
|
system.cpu2.dtb.data_accesses 349037 # DTB accesses
|
|
system.cpu2.itb.fetch_hits 552522 # ITB hits
|
|
system.cpu2.itb.fetch_misses 5239 # ITB misses
|
|
system.cpu2.itb.fetch_acv 186 # ITB acv
|
|
system.cpu2.itb.fetch_accesses 557761 # ITB accesses
|
|
system.cpu2.itb.read_hits 0 # DTB read hits
|
|
system.cpu2.itb.read_misses 0 # DTB read misses
|
|
system.cpu2.itb.read_acv 0 # DTB read access violations
|
|
system.cpu2.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.itb.write_hits 0 # DTB write hits
|
|
system.cpu2.itb.write_misses 0 # DTB write misses
|
|
system.cpu2.itb.write_acv 0 # DTB write access violations
|
|
system.cpu2.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.itb.data_hits 0 # DTB hits
|
|
system.cpu2.itb.data_misses 0 # DTB misses
|
|
system.cpu2.itb.data_acv 0 # DTB access violations
|
|
system.cpu2.itb.data_accesses 0 # DTB accesses
|
|
system.cpu2.numCycles 32231216 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.fetch.icacheStallCycles 9243140 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu2.fetch.Insts 40614337 # Number of instructions fetch has processed
|
|
system.cpu2.fetch.Branches 10791255 # Number of branches that fetch encountered
|
|
system.cpu2.fetch.predictedBranches 6954416 # Number of branches that fetch has predicted taken
|
|
system.cpu2.fetch.Cycles 20748537 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu2.fetch.SquashCycles 401448 # Number of cycles fetch has spent squashing
|
|
system.cpu2.fetch.TlbCycles 916 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu2.fetch.MiscStallCycles 10245 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu2.fetch.PendingDrainCycles 2007 # Number of cycles fetch has spent waiting on pipes to drain
|
|
system.cpu2.fetch.PendingTrapStallCycles 193088 # Number of stall cycles due to pending traps
|
|
system.cpu2.fetch.PendingQuiesceStallCycles 89379 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu2.fetch.IcacheWaitRetryStallCycles 1066 # Number of stall cycles due to full MSHR
|
|
system.cpu2.fetch.CacheLines 2772079 # Number of cache lines fetched
|
|
system.cpu2.fetch.IcacheSquashes 89992 # Number of outstanding Icache misses that were squashed
|
|
system.cpu2.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu2.fetch.rateDist::samples 30488864 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::mean 1.332104 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::stdev 2.325204 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::0 21032791 68.99% 68.99% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::1 294156 0.96% 69.95% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::2 468874 1.54% 71.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::3 5033027 16.51% 88.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::4 879823 2.89% 90.88% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::5 194768 0.64% 91.52% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::6 230051 0.75% 92.27% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::7 433078 1.42% 93.70% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::8 1922296 6.30% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::total 30488864 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.branchRate 0.334808 # Number of branch fetches per cycle
|
|
system.cpu2.fetch.rate 1.260093 # Number of inst fetches per cycle
|
|
system.cpu2.decode.IdleCycles 7572995 # Number of cycles decode is idle
|
|
system.cpu2.decode.BlockedCycles 14121086 # Number of cycles decode is blocked
|
|
system.cpu2.decode.RunCycles 7836457 # Number of cycles decode is running
|
|
system.cpu2.decode.UnblockCycles 524591 # Number of cycles decode is unblocking
|
|
system.cpu2.decode.SquashCycles 187872 # Number of cycles decode is squashing
|
|
system.cpu2.decode.BranchResolved 174587 # Number of times decode resolved a branch
|
|
system.cpu2.decode.BranchMispred 13215 # Number of times decode detected a branch misprediction
|
|
system.cpu2.decode.DecodedInsts 37262943 # Number of instructions handled by decode
|
|
system.cpu2.decode.SquashedInsts 41463 # Number of squashed instructions handled by decode
|
|
system.cpu2.rename.SquashCycles 187872 # Number of cycles rename is squashing
|
|
system.cpu2.rename.IdleCycles 7849913 # Number of cycles rename is idle
|
|
system.cpu2.rename.BlockCycles 4677015 # Number of cycles rename is blocking
|
|
system.cpu2.rename.serializeStallCycles 6609993 # count of cycles rename stalled for serializing inst
|
|
system.cpu2.rename.RunCycles 8056869 # Number of cycles rename is running
|
|
system.cpu2.rename.UnblockCycles 2861349 # Number of cycles rename is unblocking
|
|
system.cpu2.rename.RenamedInsts 36455800 # Number of instructions processed by rename
|
|
system.cpu2.rename.ROBFullEvents 58084 # Number of times rename has blocked due to ROB full
|
|
system.cpu2.rename.IQFullEvents 369048 # Number of times rename has blocked due to IQ full
|
|
system.cpu2.rename.LQFullEvents 93720 # Number of times rename has blocked due to LQ full
|
|
system.cpu2.rename.SQFullEvents 1797134 # Number of times rename has blocked due to SQ full
|
|
system.cpu2.rename.RenamedOperands 24334504 # Number of destination operands rename has renamed
|
|
system.cpu2.rename.RenameLookups 45550794 # Number of register rename lookups that rename has made
|
|
system.cpu2.rename.int_rename_lookups 45486602 # Number of integer rename lookups
|
|
system.cpu2.rename.fp_rename_lookups 59958 # Number of floating rename lookups
|
|
system.cpu2.rename.CommittedMaps 22464723 # Number of HB maps that are committed
|
|
system.cpu2.rename.UndoneMaps 1869781 # Number of HB maps that are undone due to squashing
|
|
system.cpu2.rename.serializingInsts 530990 # count of serializing insts renamed
|
|
system.cpu2.rename.tempSerializingInsts 62923 # count of temporary serializing insts renamed
|
|
system.cpu2.rename.skidInsts 3828293 # count of insts added to the skid buffer
|
|
system.cpu2.memDep0.insertedLoads 3503034 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.insertedStores 2266301 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.conflictingLoads 453472 # Number of conflicting loads.
|
|
system.cpu2.memDep0.conflictingStores 325651 # Number of conflicting stores.
|
|
system.cpu2.iq.iqInstsAdded 33952570 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu2.iq.iqNonSpecInstsAdded 679538 # Number of non-speculative instructions added to the IQ
|
|
system.cpu2.iq.iqInstsIssued 33658910 # Number of instructions issued
|
|
system.cpu2.iq.iqSquashedInstsIssued 16165 # Number of squashed instructions issued
|
|
system.cpu2.iq.iqSquashedInstsExamined 2512562 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu2.iq.iqSquashedOperandsExamined 1127430 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu2.iq.iqSquashedNonSpecRemoved 486035 # Number of squashed non-spec instructions that were removed
|
|
system.cpu2.iq.issued_per_cycle::samples 30488864 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::mean 1.103974 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::stdev 1.612784 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::0 18447860 60.51% 60.51% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::1 2702530 8.86% 69.37% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::2 1349610 4.43% 73.80% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::3 5752968 18.87% 92.67% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::4 1041424 3.42% 96.08% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::5 588365 1.93% 98.01% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::6 396836 1.30% 99.31% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::7 164449 0.54% 99.85% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::8 44822 0.15% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::total 30488864 # Number of insts issued each cycle
|
|
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntAlu 81533 21.03% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntMult 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.03% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemRead 179737 46.36% 67.39% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemWrite 126415 32.61% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.FU_type_0::No_OpClass 3114 0.01% 0.01% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntAlu 27463980 81.59% 81.60% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntMult 21318 0.06% 81.67% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.67% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatAdd 22163 0.07% 81.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatDiv 1557 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.74% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemRead 3647310 10.84% 92.57% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemWrite 2197101 6.53% 99.10% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IprAccess 302367 0.90% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::total 33658910 # Type of FU issued
|
|
system.cpu2.iq.rate 1.044295 # Inst issue rate
|
|
system.cpu2.iq.fu_busy_cnt 387685 # FU busy when requested
|
|
system.cpu2.iq.fu_busy_rate 0.011518 # FU busy rate (busy events/executed inst)
|
|
system.cpu2.iq.int_inst_queue_reads 97946508 # Number of integer instruction queue reads
|
|
system.cpu2.iq.int_inst_queue_writes 37024649 # Number of integer instruction queue writes
|
|
system.cpu2.iq.int_inst_queue_wakeup_accesses 33041720 # Number of integer instruction queue wakeup accesses
|
|
system.cpu2.iq.fp_inst_queue_reads 264026 # Number of floating instruction queue reads
|
|
system.cpu2.iq.fp_inst_queue_writes 125654 # Number of floating instruction queue writes
|
|
system.cpu2.iq.fp_inst_queue_wakeup_accesses 122549 # Number of floating instruction queue wakeup accesses
|
|
system.cpu2.iq.int_alu_accesses 33902559 # Number of integer alu accesses
|
|
system.cpu2.iq.fp_alu_accesses 140922 # Number of floating point alu accesses
|
|
system.cpu2.iew.lsq.thread0.forwLoads 200179 # Number of loads that had data forwarded from stores
|
|
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.squashedLoads 430903 # Number of loads squashed
|
|
system.cpu2.iew.lsq.thread0.ignoredResponses 1110 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu2.iew.lsq.thread0.memOrderViolation 5745 # Number of memory ordering violations
|
|
system.cpu2.iew.lsq.thread0.squashedStores 178531 # Number of stores squashed
|
|
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu2.iew.lsq.thread0.rescheduledLoads 4239 # Number of loads that were rescheduled
|
|
system.cpu2.iew.lsq.thread0.cacheBlocked 217245 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu2.iew.iewSquashCycles 187872 # Number of cycles IEW is squashing
|
|
system.cpu2.iew.iewBlockCycles 4009534 # Number of cycles IEW is blocking
|
|
system.cpu2.iew.iewUnblockCycles 206574 # Number of cycles IEW is unblocking
|
|
system.cpu2.iew.iewDispatchedInsts 35996335 # Number of instructions dispatched to IQ
|
|
system.cpu2.iew.iewDispSquashedInsts 51785 # Number of squashed instructions skipped by dispatch
|
|
system.cpu2.iew.iewDispLoadInsts 3503034 # Number of dispatched load instructions
|
|
system.cpu2.iew.iewDispStoreInsts 2266301 # Number of dispatched store instructions
|
|
system.cpu2.iew.iewDispNonSpecInsts 605122 # Number of dispatched non-speculative instructions
|
|
system.cpu2.iew.iewIQFullEvents 12947 # Number of times the IQ has become full, causing a stall
|
|
system.cpu2.iew.iewLSQFullEvents 158194 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu2.iew.memOrderViolationEvents 5745 # Number of memory order violations
|
|
system.cpu2.iew.predictedTakenIncorrect 59769 # Number of branches that were predicted taken incorrectly
|
|
system.cpu2.iew.predictedNotTakenIncorrect 133968 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu2.iew.branchMispredicts 193737 # Number of branch mispredicts detected at execute
|
|
system.cpu2.iew.iewExecutedInsts 33463084 # Number of executed instructions
|
|
system.cpu2.iew.iewExecLoadInsts 3540458 # Number of load instructions executed
|
|
system.cpu2.iew.iewExecSquashedInsts 195826 # Number of squashed instructions skipped in execute
|
|
system.cpu2.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu2.iew.exec_nop 1364227 # number of nop insts executed
|
|
system.cpu2.iew.exec_refs 5721059 # number of memory reference insts executed
|
|
system.cpu2.iew.exec_branches 7732015 # Number of branches executed
|
|
system.cpu2.iew.exec_stores 2180601 # Number of stores executed
|
|
system.cpu2.iew.exec_rate 1.038220 # Inst execution rate
|
|
system.cpu2.iew.wb_sent 33206737 # cumulative count of insts sent to commit
|
|
system.cpu2.iew.wb_count 33164269 # cumulative count of insts written-back
|
|
system.cpu2.iew.wb_producers 19394211 # num instructions producing a value
|
|
system.cpu2.iew.wb_consumers 23137569 # num instructions consuming a value
|
|
system.cpu2.iew.wb_rate 1.028949 # insts written-back per cycle
|
|
system.cpu2.iew.wb_fanout 0.838213 # average fanout of values written-back
|
|
system.cpu2.commit.commitSquashedInsts 2629534 # The number of squashed insts skipped by commit
|
|
system.cpu2.commit.commitNonSpecStalls 193503 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu2.commit.branchMispredicts 177029 # The number of times a branch was mispredicted
|
|
system.cpu2.commit.committed_per_cycle::samples 30027785 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::mean 1.109667 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::stdev 1.847605 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::0 19194769 63.92% 63.92% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::1 2226064 7.41% 71.34% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::2 1158797 3.86% 75.20% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::3 5473612 18.23% 93.42% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::4 589514 1.96% 95.39% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::5 197059 0.66% 96.04% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::6 164152 0.55% 96.59% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::7 162472 0.54% 97.13% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::8 861346 2.87% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::total 30027785 # Number of insts commited each cycle
|
|
system.cpu2.commit.committedInsts 33320829 # Number of instructions committed
|
|
system.cpu2.commit.committedOps 33320829 # Number of ops (including micro ops) committed
|
|
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu2.commit.refs 5159901 # Number of memory references committed
|
|
system.cpu2.commit.loads 3072131 # Number of loads committed
|
|
system.cpu2.commit.membars 67946 # Number of memory barriers committed
|
|
system.cpu2.commit.branches 7559828 # Number of branches committed
|
|
system.cpu2.commit.fp_insts 120718 # Number of committed floating point instructions.
|
|
system.cpu2.commit.int_insts 31821279 # Number of committed integer instructions.
|
|
system.cpu2.commit.function_calls 240082 # Number of function calls committed.
|
|
system.cpu2.commit.op_class_0::No_OpClass 1204397 3.61% 3.61% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntAlu 26540433 79.65% 83.27% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntMult 20865 0.06% 83.33% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.33% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatAdd 21723 0.07% 83.39% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.39% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.39% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.39% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatDiv 1557 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.40% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::MemRead 3140077 9.42% 92.82% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::MemWrite 2089410 6.27% 99.09% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IprAccess 302367 0.91% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::total 33320829 # Class of committed instruction
|
|
system.cpu2.commit.bw_lim_events 861346 # number cycles where commit BW limit reached
|
|
system.cpu2.rob.rob_reads 65041726 # The number of ROB reads
|
|
system.cpu2.rob.rob_writes 72360391 # The number of ROB writes
|
|
system.cpu2.timesIdled 178229 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu2.idleCycles 1742352 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu2.quiesceCycles 1747482810 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu2.committedInsts 32119546 # Number of Instructions Simulated
|
|
system.cpu2.committedOps 32119546 # Number of Ops (including micro ops) Simulated
|
|
system.cpu2.cpi 1.003477 # CPI: Cycles Per Instruction
|
|
system.cpu2.cpi_total 1.003477 # CPI: Total CPI of All Threads
|
|
system.cpu2.ipc 0.996535 # IPC: Instructions Per Cycle
|
|
system.cpu2.ipc_total 0.996535 # IPC: Total IPC of All Threads
|
|
system.cpu2.int_regfile_reads 43931463 # number of integer regfile reads
|
|
system.cpu2.int_regfile_writes 23250358 # number of integer regfile writes
|
|
system.cpu2.fp_regfile_reads 74602 # number of floating regfile reads
|
|
system.cpu2.fp_regfile_writes 74558 # number of floating regfile writes
|
|
system.cpu2.misc_regfile_reads 5374687 # number of misc regfile reads
|
|
system.cpu2.misc_regfile_writes 272957 # number of misc regfile writes
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iobus.trans_dist::ReadReq 7317 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7317 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 51364 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 51364 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5196 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 756 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18256 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 33912 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 117362 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20784 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 952 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9128 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 45584 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2707192 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 2566000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 118500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 55500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 6287500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 2120500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 86466426 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 8820000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 16844000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 41685 # number of replacements
|
|
system.iocache.tags.tagsinuse 1.261273 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 1694926915000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::tsunami.ide 1.261273 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::tsunami.ide 0.078830 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.078830 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 375525 # Number of data accesses
|
|
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
|
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
|
|
system.iocache.overall_misses::total 173 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 9575962 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 9575962 # number of ReadReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::tsunami.ide 2102569464 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 2102569464 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::tsunami.ide 9575962 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 9575962 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::tsunami.ide 9575962 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 9575962 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 55352.381503 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 55352.381503 # average ReadReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 50600.920870 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 50600.920870 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 55352.381503 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 55352.381503 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 55352.381503 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 55352.381503 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
|
system.iocache.writebacks::total 41512 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 16656 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 16656 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6075962 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 6075962 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1269053528 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 1269053528 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 6075962 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 6075962 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 6075962 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 6075962 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.400847 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 0.400847 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 86799.457143 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 86799.457143 # average ReadReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.974544 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.974544 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 86799.457143 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 86799.457143 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 86799.457143 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 86799.457143 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 337614 # number of replacements
|
|
system.l2c.tags.tagsinuse 65425.009940 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 4005222 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 402776 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 9.944043 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 54894.998559 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 2664.593878 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 2878.621970 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 441.912362 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 553.890082 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.inst 2003.349443 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.data 1987.643647 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.837631 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.040658 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.043924 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.006743 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.008452 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.inst 0.030569 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.data 0.030329 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.998306 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 713 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 6136 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 2779 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 55356 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 38412363 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 38412363 # Number of data accesses
|
|
system.l2c.WritebackDirty_hits::writebacks 835864 # number of WritebackDirty hits
|
|
system.l2c.WritebackDirty_hits::total 835864 # number of WritebackDirty hits
|
|
system.l2c.WritebackClean_hits::writebacks 963150 # number of WritebackClean hits
|
|
system.l2c.WritebackClean_hits::total 963150 # number of WritebackClean hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu2.data 9 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 13 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 90398 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 24436 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu2.data 72279 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 187113 # number of ReadExReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu0.inst 504325 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu1.inst 122994 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu2.inst 322528 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::total 949847 # number of ReadCleanReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 485259 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 78708 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu2.data 253716 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 817683 # number of ReadSharedReq hits
|
|
system.l2c.demand_hits::cpu0.inst 504325 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 575657 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 122994 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 103144 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 322528 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 325995 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1954643 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 504325 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 575657 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 122994 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 103144 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 322528 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 325995 # number of overall hits
|
|
system.l2c.overall_hits::total 1954643 # number of overall hits
|
|
system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2.data 14 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 22 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 74645 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 13952 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 27191 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 115788 # number of ReadExReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu0.inst 7793 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu1.inst 2219 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu2.inst 4231 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::total 14243 # number of ReadCleanReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 250829 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 10193 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu2.data 12429 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 273451 # number of ReadSharedReq misses
|
|
system.l2c.demand_misses::cpu0.inst 7793 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 325474 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 2219 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 24145 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 4231 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 39620 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 403482 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 7793 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 325474 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 2219 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 24145 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 4231 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 39620 # number of overall misses
|
|
system.l2c.overall_misses::total 403482 # number of overall misses
|
|
system.l2c.UpgradeReq_miss_latency::cpu2.data 551000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 551000 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu2.data 77500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 77500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 1777468000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 3688796500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 5466264500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 293360500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 567162500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::total 860523000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.data 1287741500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu2.data 1552243000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 2839984500 # number of ReadSharedReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 293360500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 3065209500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.inst 567162500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.data 5241039500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 9166772000 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 293360500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 3065209500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.inst 567162500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.data 5241039500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 9166772000 # number of overall miss cycles
|
|
system.l2c.WritebackDirty_accesses::writebacks 835864 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackDirty_accesses::total 835864 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::writebacks 963150 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::total 963150 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu2.data 23 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 35 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu2.data 3 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 165043 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 38388 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2.data 99470 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 302901 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu0.inst 512118 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu1.inst 125213 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu2.inst 326759 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::total 964090 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 736088 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 88901 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu2.data 266145 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 1091134 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 512118 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 901131 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 125213 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 127289 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.inst 326759 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.data 365615 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2358125 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 512118 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 901131 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 125213 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 127289 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.inst 326759 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.data 365615 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2358125 # number of overall (read+write) accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.608696 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.628571 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.333333 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.452276 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.363447 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2.data 0.273359 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.382264 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.015217 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.017722 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.012948 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::total 0.014774 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.340760 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.114656 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.046700 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.250612 # miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.015217 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.361184 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.017722 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.189686 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.inst 0.012948 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.data 0.108365 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.171103 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.015217 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.361184 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.017722 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.189686 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.inst 0.012948 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.data 0.108365 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.171103 # miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 39357.142857 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 25045.454545 # average UpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 77500 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 38750 # average SCUpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 127398.795872 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 135662.406679 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 47209.248800 # average ReadExReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132203.920685 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 134049.279130 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::total 60417.257600 # average ReadCleanReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 126335.867752 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 124888.808432 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 10385.716271 # average ReadSharedReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 132203.920685 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 126950.072479 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.inst 134049.279130 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.data 132282.672892 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 22719.159715 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 132203.920685 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 126950.072479 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.inst 134049.279130 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.data 132282.672892 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 22719.159715 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 75211 # number of writebacks
|
|
system.l2c.writebacks::total 75211 # number of writebacks
|
|
system.l2c.UpgradeReq_mshr_misses::cpu2.data 14 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 1 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 13952 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 27191 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 41143 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2219 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 4231 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::total 6450 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 10193 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu2.data 12429 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::total 22622 # number of ReadSharedReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 2219 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 24145 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.inst 4231 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.data 39620 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 70215 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 2219 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 24145 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.inst 4231 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.data 39620 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 70215 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 1329 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu2.data 1323 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::total 2652 # number of ReadReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 1618 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu2.data 1898 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::total 3516 # number of WriteReq MSHR uncacheable
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 2947 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu2.data 3221 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::total 6168 # number of overall MSHR uncacheable misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 960500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 960500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 67500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 67500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1637948000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 3416886500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 5054834500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 271170500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 524851004 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::total 796021504 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 1185811500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1461164000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::total 2646975500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 271170500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 2823759500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.inst 524851004 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.data 4878050500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 8497831504 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 271170500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 2823759500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.inst 524851004 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.data 4878050500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 8497831504 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 276798000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 281540000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 558338000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 353901000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 402187000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 756088000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 630699000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 683727000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 1314426000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.608696 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.333333 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.363447 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.273359 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.135830 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017722 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012948 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006690 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.114656 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.046700 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.020733 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017722 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.189686 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012948 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.108365 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.029776 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017722 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.189686 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012948 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.108365 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.029776 # mshr miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68607.142857 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68607.142857 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 67500 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117398.795872 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 125662.406679 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 122860.134166 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122203.920685 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 124048.925550 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123414.186667 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 116335.867752 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 117560.865717 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 117008.907258 # average ReadSharedReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122203.920685 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 116950.072479 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 124048.925550 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123120.911156 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 121025.870597 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122203.920685 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 116950.072479 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 124048.925550 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123120.911156 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 121025.870597 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 208275.395034 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 212804.232804 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 210534.690799 # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218727.441286 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211900.421496 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 215042.093288 # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 214013.912453 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 212271.654766 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 213104.085603 # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 7144 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 294755 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 9812 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 9812 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 116723 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 261851 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 160 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 116 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 115650 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 115650 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 287867 # Transaction distribution
|
|
system.membus.trans_dist::BadAddressError 256 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateResp 24896 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33912 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143238 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 512 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 1177662 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108424 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 108424 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1286086 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45584 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30604608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 30650192 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 33314512 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 160 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 840765 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 840765 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 840765 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 11148000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 350987320 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 315000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 374958750 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 368038 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.snoop_filter.tot_requests 4714924 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 2357142 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 1609 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 1129 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 1129 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2062215 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 9812 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 9812 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackDirty 879068 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackClean 963447 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 600902 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 35 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 39 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 302901 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 302901 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadCleanReq 964138 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 1091204 # Transaction distribution
|
|
system.toL2Bus.trans_dist::BadAddressError 256 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateReq 16656 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2891696 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4215380 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 7107076 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 123363712 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142746256 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 266109968 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 421211 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 4208443 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 0.000983 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.031334 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 4204307 99.90% 99.90% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 4136 0.10% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 4208443 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 1783289500 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 100962 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 678414167 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 743545456 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
|
|
system.cpu2.kern.mode_switch::kernel 0 # number of protection mode switches
|
|
system.cpu2.kern.mode_switch::user 0 # number of protection mode switches
|
|
system.cpu2.kern.mode_switch::idle 0 # number of protection mode switches
|
|
system.cpu2.kern.mode_good::kernel 0
|
|
system.cpu2.kern.mode_good::user 0
|
|
system.cpu2.kern.mode_good::idle 0
|
|
system.cpu2.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
|
|
system.cpu2.kern.mode_switch_good::user nan # fraction of useful protection mode switches
|
|
system.cpu2.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
|
|
system.cpu2.kern.mode_switch_good::total nan # fraction of useful protection mode switches
|
|
system.cpu2.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
|
|
system.cpu2.kern.mode_ticks::user 0 # number of ticks spent at the given mode
|
|
system.cpu2.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
|
|
system.cpu2.kern.swap_context 0 # number of times the context was actually changed
|
|
|
|
---------- End Simulation Statistics ----------
|