a8b03e4d01
arch/alpha/isa/decoder.isa:
Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model.
arch/alpha/isa/pal.isa:
Allow IPR instructions to have flags.
base/traceflags.py:
Include new trace flags from the two new CPU models.
cpu/SConscript:
Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next).
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Update to the BaseDynInst for the new models.
--HG--
extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
114 lines
4.1 KiB
C++
114 lines
4.1 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_SCOREBOARD_HH__
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#define __CPU_O3_SCOREBOARD_HH__
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#include <iostream>
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#include <utility>
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#include <vector>
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#include "arch/alpha/isa_traits.hh"
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#include "base/trace.hh"
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#include "base/traceflags.hh"
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#include "cpu/o3/comm.hh"
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/**
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* Implements a simple scoreboard to track which registers are ready.
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* This class assumes that the fp registers start, index wise, right after
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* the integer registers. The misc. registers start, index wise, right after
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* the fp registers.
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* @todo: Fix up handling of the zero register in case the decoder does not
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* automatically make insts that write the zero register into nops.
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*/
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class Scoreboard
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{
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public:
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/** Constructs a scoreboard.
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* @param activeThreads The number of active threads.
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* @param _numLogicalIntRegs Number of logical integer registers.
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* @param _numPhysicalIntRegs Number of physical integer registers.
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* @param _numLogicalFloatRegs Number of logical fp registers.
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* @param _numPhysicalFloatRegs Number of physical fp registers.
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* @param _numMiscRegs Number of miscellaneous registers.
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* @param _zeroRegIdx Index of the zero register.
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*/
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Scoreboard(unsigned activeThreads,
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unsigned _numLogicalIntRegs,
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unsigned _numPhysicalIntRegs,
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unsigned _numLogicalFloatRegs,
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unsigned _numPhysicalFloatRegs,
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unsigned _numMiscRegs,
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unsigned _zeroRegIdx);
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/** Destructor. */
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~Scoreboard() {}
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/** Returns the name of the scoreboard. */
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std::string name() const;
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/** Checks if the register is ready. */
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bool getReg(PhysRegIndex ready_reg);
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/** Sets the register as ready. */
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void setReg(PhysRegIndex phys_reg);
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/** Sets the register as not ready. */
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void unsetReg(PhysRegIndex ready_reg);
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private:
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/** Scoreboard of physical integer registers, saying whether or not they
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* are ready.
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*/
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std::vector<bool> regScoreBoard;
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/** Number of logical integer registers. */
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int numLogicalIntRegs;
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/** Number of physical integer registers. */
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int numPhysicalIntRegs;
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/** Number of logical floating point registers. */
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int numLogicalFloatRegs;
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/** Number of physical floating point registers. */
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int numPhysicalFloatRegs;
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/** Number of miscellaneous registers. */
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int numMiscRegs;
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/** Number of logical integer + float registers. */
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int numLogicalRegs;
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/** Number of physical integer + float registers. */
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int numPhysicalRegs;
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/** The logical index of the zero register. */
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int zeroRegIdx;
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};
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#endif
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