a514bf2150
cpu/activity.cc:
cpu/activity.hh:
cpu/o3/alpha_cpu.hh:
Updates to include comments.
cpu/base_dyn_inst.cc:
Remove call to thread->misspeculating(), as it's never actually misspeculating.
--HG--
extra : convert_revision : 86574d684770fac9b480475acca048ea418cdac3
262 lines
8.8 KiB
C++
262 lines
8.8 KiB
C++
/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_MEM_DEP_UNIT_HH__
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#define __CPU_O3_MEM_DEP_UNIT_HH__
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#include <list>
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#include <set>
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#include "base/hashmap.hh"
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#include "base/refcnt.hh"
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#include "base/statistics.hh"
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#include "cpu/inst_seq.hh"
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struct SNHash {
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size_t operator() (const InstSeqNum &seq_num) const {
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unsigned a = (unsigned)seq_num;
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unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
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return hash;
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}
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};
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template <class Impl>
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class InstructionQueue;
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/**
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* Memory dependency unit class. This holds the memory dependence predictor.
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* As memory operations are issued to the IQ, they are also issued to this
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* unit, which then looks up the prediction as to what they are dependent
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* upon. This unit must be checked prior to a memory operation being able
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* to issue. Although this is templated, it's somewhat hard to make a generic
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* memory dependence unit. This one is mostly for store sets; it will be
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* quite limited in what other memory dependence predictions it can also
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* utilize. Thus this class should be most likely be rewritten for other
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* dependence prediction schemes.
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*/
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template <class MemDepPred, class Impl>
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class MemDepUnit {
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public:
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typedef typename Impl::Params Params;
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typedef typename Impl::DynInstPtr DynInstPtr;
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/** Empty constructor. Must call init() prior to using in this case. */
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MemDepUnit() {}
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/** Constructs a MemDepUnit with given parameters. */
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MemDepUnit(Params *params);
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/** Frees up any memory allocated. */
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~MemDepUnit();
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/** Returns the name of the memory dependence unit. */
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std::string name() const;
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/** Initializes the unit with parameters and a thread id. */
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void init(Params *params, int tid);
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/** Registers statistics. */
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void regStats();
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/** Switches out the memory dependence predictor. */
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void switchOut();
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/** Takes over from another CPU's thread. */
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void takeOverFrom();
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/** Sets the pointer to the IQ. */
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void setIQ(InstructionQueue<Impl> *iq_ptr);
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/** Inserts a memory instruction. */
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void insert(DynInstPtr &inst);
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/** Inserts a non-speculative memory instruction. */
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void insertNonSpec(DynInstPtr &inst);
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/** Inserts a barrier instruction. */
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void insertBarrier(DynInstPtr &barr_inst);
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/** Indicate that an instruction has its registers ready. */
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void regsReady(DynInstPtr &inst);
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/** Indicate that a non-speculative instruction is ready. */
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void nonSpecInstReady(DynInstPtr &inst);
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/** Reschedules an instruction to be re-executed. */
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void reschedule(DynInstPtr &inst);
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/** Replays all instructions that have been rescheduled by moving them to
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* the ready list.
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*/
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void replay(DynInstPtr &inst);
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/** Completes a memory instruction. */
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void completed(DynInstPtr &inst);
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/** Completes a barrier instruction. */
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void completeBarrier(DynInstPtr &inst);
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/** Wakes any dependents of a memory instruction. */
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void wakeDependents(DynInstPtr &inst);
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/** Squashes all instructions up until a given sequence number for a
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* specific thread.
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*/
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void squash(const InstSeqNum &squashed_num, unsigned tid);
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/** Indicates an ordering violation between a store and a younger load. */
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void violation(DynInstPtr &store_inst, DynInstPtr &violating_load);
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/** Issues the given instruction */
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void issue(DynInstPtr &inst);
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/** Debugging function to dump the lists of instructions. */
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void dumpLists();
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private:
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typedef typename std::list<DynInstPtr>::iterator ListIt;
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class MemDepEntry;
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typedef RefCountingPtr<MemDepEntry> MemDepEntryPtr;
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/** Memory dependence entries that track memory operations, marking
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* when the instruction is ready to execute and what instructions depend
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* upon it.
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*/
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class MemDepEntry : public RefCounted {
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public:
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/** Constructs a memory dependence entry. */
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MemDepEntry(DynInstPtr &new_inst)
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: inst(new_inst), regsReady(false), memDepReady(false),
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completed(false), squashed(false)
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{
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#ifdef DEBUG
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++memdep_count;
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DPRINTF(MemDepUnit, "Memory dependency entry created. "
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"memdep_count=%i\n", memdep_count);
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#endif
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}
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/** Frees any pointers. */
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~MemDepEntry()
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{
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for (int i = 0; i < dependInsts.size(); ++i) {
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dependInsts[i] = NULL;
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}
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#ifdef DEBUG
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--memdep_count;
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DPRINTF(MemDepUnit, "Memory dependency entry deleted. "
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"memdep_count=%i\n", memdep_count);
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#endif
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}
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/** Returns the name of the memory dependence entry. */
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std::string name() const { return "memdepentry"; }
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/** The instruction being tracked. */
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DynInstPtr inst;
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/** The iterator to the instruction's location inside the list. */
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ListIt listIt;
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/** A vector of any dependent instructions. */
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std::vector<MemDepEntryPtr> dependInsts;
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/** If the registers are ready or not. */
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bool regsReady;
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/** If all memory dependencies have been satisfied. */
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bool memDepReady;
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/** If the instruction is completed. */
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bool completed;
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/** If the instruction is squashed. */
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bool squashed;
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/** For debugging. */
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#ifdef DEBUG
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static int memdep_count;
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static int memdep_insert;
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static int memdep_erase;
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#endif
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};
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/** Finds the memory dependence entry in the hash map. */
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inline MemDepEntryPtr &findInHash(const DynInstPtr &inst);
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/** Moves an entry to the ready list. */
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inline void moveToReady(MemDepEntryPtr &ready_inst_entry);
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typedef m5::hash_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash;
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typedef typename MemDepHash::iterator MemDepHashIt;
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/** A hash map of all memory dependence entries. */
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MemDepHash memDepHash;
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/** A list of all instructions in the memory dependence unit. */
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std::list<DynInstPtr> instList[Impl::MaxThreads];
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/** A list of all instructions that are going to be replayed. */
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std::list<DynInstPtr> instsToReplay;
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/** The memory dependence predictor. It is accessed upon new
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* instructions being added to the IQ, and responds by telling
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* this unit what instruction the newly added instruction is dependent
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* upon.
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*/
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MemDepPred depPred;
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/** Is there an outstanding load barrier that loads must wait on. */
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bool loadBarrier;
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/** The sequence number of the load barrier. */
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InstSeqNum loadBarrierSN;
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/** Is there an outstanding store barrier that loads must wait on. */
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bool storeBarrier;
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/** The sequence number of the store barrier. */
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InstSeqNum storeBarrierSN;
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/** Pointer to the IQ. */
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InstructionQueue<Impl> *iqPtr;
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/** The thread id of this memory dependence unit. */
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int id;
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/** Stat for number of inserted loads. */
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Stats::Scalar<> insertedLoads;
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/** Stat for number of inserted stores. */
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Stats::Scalar<> insertedStores;
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/** Stat for number of conflicting loads that had to wait for a store. */
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Stats::Scalar<> conflictingLoads;
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/** Stat for number of conflicting stores that had to wait for a store. */
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Stats::Scalar<> conflictingStores;
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};
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#endif // __CPU_O3_MEM_DEP_UNIT_HH__
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