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gem5/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
Steve Reinhardt 7b40c36fbd Update stats for new single bad-address responder. 
Mostly just config.ini updates, though the different response
latency for bad addresses caused very minor timing changes
in the O3 Linux boot tests.
2009-04-22 01:55:52 -04:00

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[root]
type=Root
children=system
dummy=0
[system]
type=System
children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
mem_mode=atomic
physmem=system.physmem
[system.cpu0]
type=AtomicSimpleCPU
children=dcache dtb icache itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu0.dtb
function_trace=false
function_trace_start=0
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu0.tracer
width=1
workload=system.cpu0.workload
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mshrs=4
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.port[2]
[system.cpu0.dtb]
type=SparcTLB
size=64
[system.cpu0.icache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mshrs=4
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.port[1]
[system.cpu0.itb]
type=SparcTLB
size=64
[system.cpu0.tracer]
type=ExeTracer
[system.cpu0.workload]
type=LiveProcess
cmd=test_atomic 4
cwd=
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.cpu1]
type=AtomicSimpleCPU
children=dcache dtb icache itb tracer
checker=Null
clock=500
cpu_id=1
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu1.dtb
function_trace=false
function_trace_start=0
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu1.tracer
width=1
workload=system.cpu0.workload
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mshrs=4
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.port[4]
[system.cpu1.dtb]
type=SparcTLB
size=64
[system.cpu1.icache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mshrs=4
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.port[3]
[system.cpu1.itb]
type=SparcTLB
size=64
[system.cpu1.tracer]
type=ExeTracer
[system.cpu2]
type=AtomicSimpleCPU
children=dcache dtb icache itb tracer
checker=Null
clock=500
cpu_id=2
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu2.dtb
function_trace=false
function_trace_start=0
itb=system.cpu2.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu2.tracer
width=1
workload=system.cpu0.workload
dcache_port=system.cpu2.dcache.cpu_side
icache_port=system.cpu2.icache.cpu_side
[system.cpu2.dcache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mshrs=4
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.dcache_port
mem_side=system.toL2Bus.port[6]
[system.cpu2.dtb]
type=SparcTLB
size=64
[system.cpu2.icache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mshrs=4
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.icache_port
mem_side=system.toL2Bus.port[5]
[system.cpu2.itb]
type=SparcTLB
size=64
[system.cpu2.tracer]
type=ExeTracer
[system.cpu3]
type=AtomicSimpleCPU
children=dcache dtb icache itb tracer
checker=Null
clock=500
cpu_id=3
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu3.dtb
function_trace=false
function_trace_start=0
itb=system.cpu3.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
system=system
tracer=system.cpu3.tracer
width=1
workload=system.cpu0.workload
dcache_port=system.cpu3.dcache.cpu_side
icache_port=system.cpu3.icache.cpu_side
[system.cpu3.dcache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mshrs=4
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.dcache_port
mem_side=system.toL2Bus.port[8]
[system.cpu3.dtb]
type=SparcTLB
size=64
[system.cpu3.icache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mshrs=4
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
tgts_per_mshr=8
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.icache_port
mem_side=system.toL2Bus.port[7]
[system.cpu3.itb]
type=SparcTLB
size=64
[system.cpu3.tracer]
type=ExeTracer
[system.l2c]
type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mshrs=92
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
tgts_per_mshr=16
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
mem_side=system.membus.port[0]
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
header_cycles=1
responder_set=false
width=64
port=system.l2c.mem_side system.physmem.port[0]
[system.physmem]
type=PhysicalMemory
file=
latency=30000
latency_var=0
null=false
range=0:1073741823
zero=false
port=system.membus.port[1]
[system.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
header_cycles=1
responder_set=false
width=64
port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
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