273 lines
12 KiB
Python
273 lines
12 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Brad Beckmann
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import math
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from Ruby import create_topology
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from Ruby import send_evicts
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#
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# Declare caches used by the protocol
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#
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class L1Cache(RubyCache): pass
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class L2Cache(RubyCache): pass
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def define_options(parser):
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parser.add_option("--l1-retries", type="int", default=1,
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help="Token_CMP: # of l1 retries before going persistent")
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parser.add_option("--timeout-latency", type="int", default=300,
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help="Token_CMP: cycles until issuing again");
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parser.add_option("--disable-dyn-timeouts", action="store_true",
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help="Token_CMP: disable dyanimc timeouts, use fixed latency instead")
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parser.add_option("--allow-atomic-migration", action="store_true",
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help="allow migratory sharing for atomic only accessed blocks")
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def create_system(options, full_system, system, dma_ports, ruby_system):
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if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
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panic("This script requires the MOESI_CMP_token protocol to be built.")
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#
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# number of tokens that the owner passes to requests so that shared blocks can
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# respond to read requests
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#
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n_tokens = options.num_cpus + 1
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cpu_sequencers = []
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#
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# The ruby network creation expects the list of nodes in the system to be
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# consistent with the NetDest list. Therefore the l1 controller nodes must be
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# listed before the directory nodes and directory nodes before dma nodes, etc.
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#
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l1_cntrl_nodes = []
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l2_cntrl_nodes = []
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dir_cntrl_nodes = []
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dma_cntrl_nodes = []
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#
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# Must create the individual controllers before the network to ensure the
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# controller constructors are called before the network constructor
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#
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l2_bits = int(math.log(options.num_l2caches, 2))
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block_size_bits = int(math.log(options.cacheline_size, 2))
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for i in xrange(options.num_cpus):
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#
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# First create the Ruby objects associated with this cpu
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#
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l1i_cache = L1Cache(size = options.l1i_size,
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assoc = options.l1i_assoc,
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start_index_bit = block_size_bits)
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l1d_cache = L1Cache(size = options.l1d_size,
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assoc = options.l1d_assoc,
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start_index_bit = block_size_bits)
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l1_cntrl = L1Cache_Controller(version = i,
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L1Icache = l1i_cache,
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L1Dcache = l1d_cache,
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l2_select_num_bits = l2_bits,
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N_tokens = n_tokens,
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retry_threshold = \
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options.l1_retries,
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fixed_timeout_latency = \
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options.timeout_latency,
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dynamic_timeout_enabled = \
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not options.disable_dyn_timeouts,
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no_mig_atomic = not \
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options.allow_atomic_migration,
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send_evictions = send_evicts(options),
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transitions_per_cycle = options.ports,
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clk_domain=system.cpu[i].clk_domain,
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ruby_system = ruby_system)
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cpu_seq = RubySequencer(version = i,
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icache = l1i_cache,
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dcache = l1d_cache,
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clk_domain=system.cpu[i].clk_domain,
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ruby_system = ruby_system)
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l1_cntrl.sequencer = cpu_seq
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exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
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# Add controllers and sequencers to the appropriate lists
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cpu_sequencers.append(cpu_seq)
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l1_cntrl_nodes.append(l1_cntrl)
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# Connect the L1 controllers and the network
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l1_cntrl.requestFromL1Cache = MessageBuffer()
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l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave
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l1_cntrl.responseFromL1Cache = MessageBuffer()
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l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave
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l1_cntrl.persistentFromL1Cache = MessageBuffer(ordered = True)
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l1_cntrl.persistentFromL1Cache.master = ruby_system.network.slave
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l1_cntrl.mandatoryQueue = MessageBuffer()
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l1_cntrl.requestToL1Cache = MessageBuffer()
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l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
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l1_cntrl.responseToL1Cache = MessageBuffer()
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l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
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l1_cntrl.persistentToL1Cache = MessageBuffer(ordered = True)
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l1_cntrl.persistentToL1Cache.slave = ruby_system.network.master
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l2_index_start = block_size_bits + l2_bits
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for i in xrange(options.num_l2caches):
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#
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# First create the Ruby objects associated with this cpu
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#
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l2_cache = L2Cache(size = options.l2_size,
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assoc = options.l2_assoc,
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start_index_bit = l2_index_start)
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l2_cntrl = L2Cache_Controller(version = i,
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L2cache = l2_cache,
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N_tokens = n_tokens,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
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l2_cntrl_nodes.append(l2_cntrl)
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# Connect the L2 controllers and the network
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l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer()
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l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave
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l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
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l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
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l2_cntrl.responseFromL2Cache = MessageBuffer()
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l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
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l2_cntrl.GlobalRequestToL2Cache = MessageBuffer()
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l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master
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l2_cntrl.L1RequestToL2Cache = MessageBuffer()
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l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
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l2_cntrl.responseToL2Cache = MessageBuffer()
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l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
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l2_cntrl.persistentToL2Cache = MessageBuffer(ordered = True)
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l2_cntrl.persistentToL2Cache.slave = ruby_system.network.master
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phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
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assert(phys_mem_size % options.num_dirs == 0)
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mem_module_size = phys_mem_size / options.num_dirs
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# Run each of the ruby memory controllers at a ratio of the frequency of
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# the ruby system
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# clk_divider value is a fix to pass regression.
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ruby_system.memctrl_clk_domain = DerivedClockDomain(
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clk_domain=ruby_system.clk_domain,
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clk_divider=3)
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for i in xrange(options.num_dirs):
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dir_size = MemorySize('0B')
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dir_size.value = mem_module_size
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dir_cntrl = Directory_Controller(version = i,
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directory = RubyDirectoryMemory(
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version = i, size = dir_size),
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l2_select_num_bits = l2_bits,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
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dir_cntrl_nodes.append(dir_cntrl)
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# Connect the directory controllers and the network
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dir_cntrl.requestToDir = MessageBuffer()
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dir_cntrl.requestToDir.slave = ruby_system.network.master
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dir_cntrl.responseToDir = MessageBuffer()
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dir_cntrl.responseToDir.slave = ruby_system.network.master
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dir_cntrl.persistentToDir = MessageBuffer(ordered = True)
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dir_cntrl.persistentToDir.slave = ruby_system.network.master
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dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
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dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
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dir_cntrl.requestFromDir = MessageBuffer()
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dir_cntrl.requestFromDir.master = ruby_system.network.slave
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dir_cntrl.responseFromDir = MessageBuffer()
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dir_cntrl.responseFromDir.master = ruby_system.network.slave
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dir_cntrl.persistentFromDir = MessageBuffer(ordered = True)
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dir_cntrl.persistentFromDir.master = ruby_system.network.slave
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dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True)
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dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
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dir_cntrl.responseFromMemory = MessageBuffer()
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for i, dma_port in enumerate(dma_ports):
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#
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# Create the Ruby objects associated with the dma controller
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#
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dma_seq = DMASequencer(version = i,
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ruby_system = ruby_system,
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slave = dma_port)
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dma_cntrl = DMA_Controller(version = i,
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dma_sequencer = dma_seq,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
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dma_cntrl_nodes.append(dma_cntrl)
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# Connect the dma controller to the network
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dma_cntrl.mandatoryQueue = MessageBuffer()
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dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
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dma_cntrl.responseFromDir.slave = ruby_system.network.master
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dma_cntrl.reqToDirectory = MessageBuffer()
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dma_cntrl.reqToDirectory.master = ruby_system.network.slave
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all_cntrls = l1_cntrl_nodes + \
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l2_cntrl_nodes + \
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dir_cntrl_nodes + \
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dma_cntrl_nodes
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# Create the io controller and the sequencer
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if full_system:
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io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
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ruby_system._io_port = io_seq
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io_controller = DMA_Controller(version = len(dma_ports),
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dma_sequencer = io_seq,
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ruby_system = ruby_system)
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ruby_system.io_controller = io_controller
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# Connect the dma controller to the network
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io_controller.mandatoryQueue = MessageBuffer()
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io_controller.responseFromDir = MessageBuffer(ordered = True)
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io_controller.responseFromDir.slave = ruby_system.network.master
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io_controller.reqToDirectory = MessageBuffer()
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io_controller.reqToDirectory.master = ruby_system.network.slave
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all_cntrls = all_cntrls + [io_controller]
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topology = create_topology(all_cntrls, options)
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return (cpu_sequencers, dir_cntrl_nodes, topology)
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