sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity
gem5/tests/long/70.twolf/ref/x86/linux/simple-timing
History
Steve Reinhardt 9e45ada171 stats: update stats for preceding coherence changes 
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
2010-09-09 14:40:19 -04:00
..
config.ini stats: update stats for preceding coherence changes 2010-09-09 14:40:19 -04:00
simerr Update stats for new prefetching fixes. 2009-02-16 12:09:45 -05:00
simout stats: update stats for preceding coherence changes 2010-09-09 14:40:19 -04:00
smred.out X86: Add x86 reference output for the timing CPU. 2008-11-09 21:57:15 -08:00
smred.pin X86: Add x86 reference output for the timing CPU. 2008-11-09 21:57:15 -08:00
smred.pl1 X86: Add x86 reference output for the timing CPU. 2008-11-09 21:57:15 -08:00
smred.pl2 X86: Add x86 reference output for the timing CPU. 2008-11-09 21:57:15 -08:00
smred.sav X86: Add x86 reference output for the timing CPU. 2008-11-09 21:57:15 -08:00
smred.sv2 X86: Add x86 reference output for the timing CPU. 2008-11-09 21:57:15 -08:00
smred.twf X86: Add x86 reference output for the timing CPU. 2008-11-09 21:57:15 -08:00
stats.txt stats: update stats for preceding coherence changes 2010-09-09 14:40:19 -04:00