gem5/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
Andreas Hansson 54227f9e57 Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
2012-10-15 08:09:54 -04:00

377 lines
43 KiB
Text

---------- Begin Simulation Statistics ----------
sim_seconds 1.649901 # Number of seconds simulated
sim_ticks 1649900881000 # Number of ticks simulated
final_tick 1649900881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 669860 # Simulator instruction rate (inst/s)
host_op_rate 1238647 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1336598464 # Simulator tick rate (ticks/s)
host_mem_usage 232964 # Number of bytes of host memory used
host_seconds 1234.40 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988700 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 27359872 # Number of bytes read from this memory
system.physmem.bytes_read::total 27483456 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 123584 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 123584 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 20708480 # Number of bytes written to this memory
system.physmem.bytes_written::total 20708480 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1931 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 427498 # Number of read requests responded to by this memory
system.physmem.num_reads::total 429429 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory
system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 74904 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 16582737 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 16657641 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 74904 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 74904 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 12551348 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 12551348 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 12551348 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 74904 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 16582737 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 29208989 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 3299801762 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826877110 # Number of instructions committed
system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
system.cpu.num_int_insts 1528317558 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 3855106250 # number of times the integer registers were read
system.cpu.num_int_register_writes 1614040851 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 533262341 # number of memory refs
system.cpu.num_load_insts 384102156 # Number of load instructions
system.cpu.num_store_insts 149160185 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 3299801762 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 1253 # number of replacements
system.cpu.icache.tagsinuse 881.283724 # Cycle average of tags in use
system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 881.283724 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.430314 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.430314 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1068344252 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1068344252 # number of overall hits
system.cpu.icache.overall_hits::total 1068344252 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
system.cpu.icache.overall_misses::total 2814 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 117690500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 117690500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 117690500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 117690500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 117690500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 117690500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1068347066 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1068347066 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1068347066 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41823.205402 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 41823.205402 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 41823.205402 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 41823.205402 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 41823.205402 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 41823.205402 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112062500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 112062500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112062500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 112062500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112062500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 112062500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39823.205402 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39823.205402 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39823.205402 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 39823.205402 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39823.205402 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 39823.205402 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2514362 # number of replacements
system.cpu.dcache.tagsinuse 4086.427569 # Cycle average of tags in use
system.cpu.dcache.total_refs 530743928 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 8211722000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4086.427569 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997663 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997663 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148369157 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 530743928 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 530743928 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 530743928 # number of overall hits
system.cpu.dcache.overall_hits::total 530743928 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 31594062000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 31594062000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19100972000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 19100972000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 50695034000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 50695034000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 50695034000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 50695034000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 533262386 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 533262386 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 533262386 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 533262386 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18289.803139 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 18289.803139 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24146.535465 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 24146.535465 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20129.394256 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20129.394256 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20129.394256 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20129.394256 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 2297113 # number of writebacks
system.cpu.dcache.writebacks::total 2297113 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28139234000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 28139234000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17518884000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 17518884000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45658118000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 45658118000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45658118000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 45658118000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16289.803139 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16289.803139 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22146.535465 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22146.535465 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18129.394256 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18129.394256 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18129.394256 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18129.394256 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 403150 # number of replacements
system.cpu.l2cache.tagsinuse 29110.547277 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3572765 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 435501 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 8.203804 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 772497646000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21034.967888 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 79.712550 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 7995.866840 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.641936 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.002433 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.244014 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.888383 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 883 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1509854 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1510737 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 2297113 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 2297113 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 581106 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 581106 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 883 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2090960 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2091843 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 883 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2090960 # number of overall hits
system.cpu.l2cache.overall_hits::total 2091843 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 1931 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 217560 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 219491 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 209938 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 209938 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1931 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 427498 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 429429 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1931 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 427498 # number of overall misses
system.cpu.l2cache.overall_misses::total 429429 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100418500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11313280000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 11413698500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10916780000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 10916780000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 100418500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 22230060000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22330478500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 100418500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 22230060000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22330478500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 2297113 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 2297113 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.686212 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.125945 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.126857 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265394 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.265394 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.686212 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.169746 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.170322 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.686212 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.169746 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.170322 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52003.366132 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.735429 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.758573 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.019053 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.019053 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52003.366132 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.383628 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000.397039 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52003.366132 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.383628 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000.397039 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 323570 # number of writebacks
system.cpu.l2cache.writebacks::total 323570 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1931 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 217560 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 219491 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209938 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 209938 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1931 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 427498 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 429429 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1931 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 427498 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 429429 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 77246000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8702551000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8779797000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8397520000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8397520000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 77246000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17100071000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 17177317000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 77246000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17100071000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 17177317000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.125945 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.126857 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265394 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265394 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.169746 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.170322 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169746 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.170322 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.107198 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.694061 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.715291 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.107198 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.353218 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.365602 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.107198 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.353218 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.365602 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------