54227f9e57
This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
374 lines
43 KiB
Text
374 lines
43 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.365994 # Number of seconds simulated
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sim_ticks 365994481000 # Number of ticks simulated
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final_tick 365994481000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 452383 # Simulator instruction rate (inst/s)
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host_op_rate 796575 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1047986231 # Simulator tick rate (ticks/s)
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host_mem_usage 363904 # Number of bytes of host memory used
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host_seconds 349.24 # Real time elapsed on the host
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sim_insts 157988548 # Number of instructions simulated
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sim_ops 278192463 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 1879680 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1931392 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 51712 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 51712 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 14528 # Number of bytes written to this memory
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system.physmem.bytes_written::total 14528 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 808 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 29370 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 30178 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 227 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 227 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 141292 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 5135815 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 5277107 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 141292 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 141292 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 39695 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 39695 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 39695 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 141292 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 5135815 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 5316801 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.workload.num_syscalls 444 # Number of system calls
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system.cpu.numCycles 731988962 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 157988548 # Number of instructions committed
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system.cpu.committedOps 278192463 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 278186171 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
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system.cpu.num_func_calls 0 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
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system.cpu.num_int_insts 278186171 # number of integer instructions
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system.cpu.num_fp_insts 40 # number of float instructions
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system.cpu.num_int_register_reads 739519993 # number of times the integer registers were read
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system.cpu.num_int_register_writes 279212718 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
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system.cpu.num_mem_refs 122219135 # number of memory refs
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system.cpu.num_load_insts 90779384 # Number of load instructions
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system.cpu.num_store_insts 31439751 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 731988962 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 24 # number of replacements
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system.cpu.icache.tagsinuse 665.633473 # Cycle average of tags in use
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system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 665.633473 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 217695357 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 217695357 # number of overall hits
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system.cpu.icache.overall_hits::total 217695357 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
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system.cpu.icache.overall_misses::total 808 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 44440000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 44440000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 44440000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 44440000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 44440000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 44440000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 217696165 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 217696165 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 217696165 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42824000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 42824000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42824000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 42824000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 2062733 # number of replacements
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system.cpu.dcache.tagsinuse 4076.488929 # Cycle average of tags in use
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system.cpu.dcache.total_refs 120152368 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 58.133676 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 126079699000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 4076.488929 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.995237 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.995237 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 31333642 # number of WriteReq hits
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system.cpu.dcache.demand_hits::cpu.data 120152368 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 120152368 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 120152368 # number of overall hits
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system.cpu.dcache.overall_hits::total 120152368 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
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system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 25503766000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 25503766000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598582000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 2598582000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 28102348000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 28102348000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 28102348000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 28102348000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::cpu.data 122219197 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 122219197 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::cpu.data 122219197 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 122219197 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.347301 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.347301 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24489.741681 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 24489.741681 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::cpu.data 13596.842313 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 13596.842313 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 13596.842313 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total 13596.842313 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.writebacks::writebacks 2061794 # number of writebacks
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system.cpu.dcache.writebacks::total 2061794 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21582326000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 21582326000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386364000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386364000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23968690000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 23968690000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23968690000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 23968690000 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
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system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.347301 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.347301 # average ReadReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22489.741681 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22489.741681 # average WriteReq mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11596.842313 # average overall mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::total 11596.842313 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11596.842313 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::total 11596.842313 # average overall mshr miss latency
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 1081 # number of replacements
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system.cpu.l2cache.tagsinuse 19679.255550 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 3991053 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 30157 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 132.342508 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 19326.193704 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 210.694953 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 142.366893 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.589789 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.006430 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.004345 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.600563 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1960377 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1960377 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 2061794 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 2061794 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 77082 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 77082 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 2037459 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2037459 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 2037459 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2037459 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 343 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1151 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 29027 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 29027 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 29370 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 30178 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 808 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 29370 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 30178 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42016000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17836000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 59852000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509435000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1509435000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 42016000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 1527271000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 1569287000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 42016000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 1527271000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 1569287000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 2061794 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 2061794 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000175 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.000587 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273558 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.273558 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.014210 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.014595 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014210 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.014595 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.067971 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.067971 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.055499 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52001.027238 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.055499 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52001.027238 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 227 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 227 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 343 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1151 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29027 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 29027 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 29370 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 30178 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 29370 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 30178 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32320000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13720000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 46040000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1161080000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1161080000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32320000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1174800000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 1207120000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32320000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1174800000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1207120000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000175 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000587 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273558 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273558 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014210 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014210 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|