54227f9e57
This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
427 lines
48 KiB
Text
427 lines
48 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.793710 # Number of seconds simulated
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sim_ticks 793709507000 # Number of ticks simulated
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final_tick 793709507000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1083083 # Simulator instruction rate (inst/s)
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host_op_rate 1143775 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1512037928 # Simulator tick rate (ticks/s)
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host_mem_usage 233820 # Number of bytes of host memory used
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host_seconds 524.93 # Real time elapsed on the host
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sim_insts 568539335 # Number of instructions simulated
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sim_ops 600398272 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 39104 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 1735040 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1774144 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 39104 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 39104 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 194752 # Number of bytes written to this memory
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system.physmem.bytes_written::total 194752 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 611 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 27110 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 27721 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 3043 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 3043 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 49267 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 2185989 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2235256 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 49267 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 49267 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 245369 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 245369 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 245369 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 49267 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 2185989 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2480625 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 48 # Number of system calls
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system.cpu.numCycles 1587419014 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 568539335 # Number of instructions committed
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system.cpu.committedOps 600398272 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 533522631 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
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system.cpu.num_func_calls 1995305 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 67050634 # number of instructions that are conditional controls
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system.cpu.num_int_insts 533522631 # number of integer instructions
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system.cpu.num_fp_insts 16 # number of float instructions
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system.cpu.num_int_register_reads 3212467067 # number of times the integer registers were read
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system.cpu.num_int_register_writes 614470972 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 219173606 # number of memory refs
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system.cpu.num_load_insts 148952593 # Number of load instructions
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system.cpu.num_store_insts 70221013 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 1587419014 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 12 # number of replacements
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system.cpu.icache.tagsinuse 577.773227 # Cycle average of tags in use
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system.cpu.icache.total_refs 570073883 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 886584.576983 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 577.773227 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.282116 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.282116 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 570073883 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 570073883 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 570073883 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 570073883 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 570073883 # number of overall hits
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system.cpu.icache.overall_hits::total 570073883 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 643 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 643 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 643 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses
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system.cpu.icache.overall_misses::total 643 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 34021000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 34021000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 34021000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 34021000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 34021000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 34021000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 570074526 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 570074526 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 570074526 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 570074526 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 570074526 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 570074526 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52909.797823 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 52909.797823 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 52909.797823 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 52909.797823 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 52909.797823 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 52909.797823 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 643 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 643 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 643 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32735000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 32735000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32735000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 32735000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32735000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 32735000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50909.797823 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50909.797823 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 433468 # number of replacements
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system.cpu.dcache.tagsinuse 4094.242161 # Cycle average of tags in use
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system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 529482000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 4094.242161 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.999571 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.999571 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits
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system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits
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system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits
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system.cpu.dcache.demand_hits::cpu.data 216771818 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 216771818 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 216771818 # number of overall hits
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system.cpu.dcache.overall_hits::total 216771818 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 247748 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 437564 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses
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system.cpu.dcache.overall_misses::total 437564 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 2675478000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 2675478000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 4151654000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 4151654000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 6827132000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 6827132000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 6827132000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 6827132000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::cpu.data 217209382 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 217209382 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::cpu.data 217209382 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 217209382 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_miss_rate::total 0.003569 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14095.113162 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total 14095.113162 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16757.568174 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 16757.568174 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::cpu.data 15602.590707 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 15602.590707 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 15602.590707 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total 15602.590707 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 418219 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 418219 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 247748 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 437564 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2295846000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2295846000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3656158000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3656158000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5952004000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 5952004000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5952004000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 5952004000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003569 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12095.113162 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12095.113162 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14757.568174 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14757.568174 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13602.590707 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13602.590707 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13602.590707 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13602.590707 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 3963 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 21582.814171 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 495400 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 24559 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 20.171831 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 20943.692003 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 130.073000 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 509.049168 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.639151 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.015535 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.658655 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 184871 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 184903 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 418219 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 418219 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 225583 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 225583 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 410454 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 410486 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 410454 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 410486 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 611 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 4945 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 5556 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 22165 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 22165 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 611 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 27110 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 27721 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 611 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 27110 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 27721 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31772000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 257320000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 289092000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1152580000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1152580000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 31772000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 1409900000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 1441672000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 31772000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 1409900000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 1441672000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 418219 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 418219 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247748 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 247748 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 643 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 437564 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 438207 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 643 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 437564 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.950233 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026052 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.029172 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089466 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.089466 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.950233 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.061957 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.063260 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.950233 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.061957 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.063260 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52036.400404 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52032.397408 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52006.639616 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52006.493272 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52006.639616 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52006.493272 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 3043 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 3043 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 611 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4945 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 5556 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22165 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 22165 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 611 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 27110 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 27721 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 611 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 27110 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 27721 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24440000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 197980000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222420000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 886600000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 886600000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24440000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1084580000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 1109020000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24440000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1084580000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1109020000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026052 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.029172 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089466 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089466 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.061957 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063260 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.061957 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063260 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40036.400404 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40032.397408 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40006.639616 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40006.493272 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40006.639616 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40006.493272 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|