950 lines
108 KiB
Text
950 lines
108 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.144620 # Number of seconds simulated
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sim_ticks 144620050000 # Number of ticks simulated
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final_tick 144620050000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 65513 # Simulator instruction rate (inst/s)
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host_op_rate 109805 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 71737347 # Simulator tick rate (ticks/s)
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host_mem_usage 319696 # Number of bytes of host memory used
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host_seconds 2015.97 # Real time elapsed on the host
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sim_insts 132071192 # Number of instructions simulated
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sim_ops 221363384 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 217216 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory
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system.physmem.bytes_read::total 342656 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 217216 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 217216 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 3394 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 5354 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1501977 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 867376 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2369353 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1501977 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1501977 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1501977 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 867376 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2369353 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 5356 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 5356 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 342784 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 342784 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 131 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 288 # Per bank write bursts
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system.physmem.perBankRdBursts::1 358 # Per bank write bursts
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system.physmem.perBankRdBursts::2 449 # Per bank write bursts
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system.physmem.perBankRdBursts::3 356 # Per bank write bursts
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system.physmem.perBankRdBursts::4 330 # Per bank write bursts
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system.physmem.perBankRdBursts::5 328 # Per bank write bursts
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system.physmem.perBankRdBursts::6 400 # Per bank write bursts
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system.physmem.perBankRdBursts::7 378 # Per bank write bursts
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system.physmem.perBankRdBursts::8 340 # Per bank write bursts
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system.physmem.perBankRdBursts::9 277 # Per bank write bursts
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system.physmem.perBankRdBursts::10 231 # Per bank write bursts
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system.physmem.perBankRdBursts::11 276 # Per bank write bursts
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system.physmem.perBankRdBursts::12 208 # Per bank write bursts
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system.physmem.perBankRdBursts::13 466 # Per bank write bursts
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system.physmem.perBankRdBursts::14 385 # Per bank write bursts
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system.physmem.perBankRdBursts::15 286 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 144620007000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 5356 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 4298 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 873 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 161 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1043 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 326.933845 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 193.223116 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 334.208962 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 368 35.28% 35.28% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 248 23.78% 59.06% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 102 9.78% 68.84% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 58 5.56% 74.40% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 42 4.03% 78.43% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 59 5.66% 84.08% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 17 1.63% 85.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 23 2.21% 87.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 126 12.08% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1043 # Bytes accessed per row activation
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system.physmem.totQLat 35519000 # Total ticks spent queuing
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system.physmem.totMemAccLat 135944000 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 26780000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 6631.63 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 25381.63 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.02 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 4304 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 80.36 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 27001494.96 # Average gap between requests
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system.physmem.pageHitRate 80.36 # Row buffer hit rate, read and write combined
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system.physmem.memoryStateTime::IDLE 138334279250 # Time in different power states
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system.physmem.memoryStateTime::REF 4828980000 # Time in different power states
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::ACT 1451861250 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.membus.throughput 2368911 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 3823 # Transaction distribution
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system.membus.trans_dist::ReadResp 3820 # Transaction distribution
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system.membus.trans_dist::UpgradeReq 131 # Transaction distribution
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system.membus.trans_dist::UpgradeResp 131 # Transaction distribution
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system.membus.trans_dist::ReadExReq 1533 # Transaction distribution
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system.membus.trans_dist::ReadExResp 1533 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10971 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10971 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 10971 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342592 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 342592 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 342592 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 6960500 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.respLayer1.occupancy 50659869 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.branchPred.lookups 18663045 # Number of BP lookups
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system.cpu.branchPred.condPredicted 18663045 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 1489785 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 11444584 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 10797822 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 94.348750 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 1319901 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 22895 # Number of incorrect RAS predictions.
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system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
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system.cpu.workload.num_syscalls 400 # Number of system calls
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system.cpu.numCycles 289523031 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 23473938 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 206858197 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 18663045 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 12117723 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 54247835 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 15552938 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 178336695 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 1340 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 7706 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 22368694 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 223698 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 269869756 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.267902 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.756065 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 217061517 80.43% 80.43% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 2847740 1.06% 81.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 2315002 0.86% 82.35% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 2640494 0.98% 83.32% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 3217056 1.19% 84.52% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 3387561 1.26% 85.77% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 3839682 1.42% 87.19% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 2560696 0.95% 88.14% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 32000008 11.86% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 269869756 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.064461 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.714479 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 36939117 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 167279649 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 41594778 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 10253994 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 13802218 # Number of cycles decode is squashing
|
|
system.cpu.decode.DecodedInsts 336245393 # Number of instructions handled by decode
|
|
system.cpu.rename.SquashCycles 13802218 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 45020160 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 116775107 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 31642 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 42714880 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 51525749 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 329872428 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 11092 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 26167242 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 22759273 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RenamedOperands 382595093 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 918331708 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 606342575 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 4133173 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 123165643 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 2073 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 2073 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 105277588 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 84554246 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 30134710 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 58533931 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 19035455 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 322937953 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 4364 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 260608849 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 112553 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 101196304 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 210593531 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 3119 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 269869756 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.965684 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.342187 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 143519297 53.18% 53.18% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 55647203 20.62% 73.80% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 34229884 12.68% 86.48% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 19073202 7.07% 93.55% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 10874136 4.03% 97.58% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 4113724 1.52% 99.11% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 1802263 0.67% 99.77% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 476846 0.18% 99.95% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 133201 0.05% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 269869756 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 125646 4.63% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 2288183 84.39% 89.02% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 297636 10.98% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 1210826 0.46% 0.46% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 162119129 62.21% 62.67% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 788294 0.30% 62.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 7035677 2.70% 65.67% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 1444684 0.55% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 65441941 25.11% 91.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 22568298 8.66% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 260608849 # Type of FU issued
|
|
system.cpu.iq.rate 0.900132 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 2711465 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.010404 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 789025856 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 420800342 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 255248449 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 4885616 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 3622403 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 2349194 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 259650836 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 2458652 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 18874838 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 27904659 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 26471 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 289699 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 9618993 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 50123 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 13802218 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 85051562 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 5443180 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 322942317 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 133815 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 84554246 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 30134710 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 2043 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 2682047 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 14716 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 289699 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 640019 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 900364 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 1540383 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 258834349 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 64663337 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1774500 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 87028906 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 14271418 # Number of branches executed
|
|
system.cpu.iew.exec_stores 22365569 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.894003 # Inst execution rate
|
|
system.cpu.iew.wb_sent 258197839 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 257597643 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 206027195 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 369217293 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.889731 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.558011 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 101647922 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 1490935 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 256067538 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.864473 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.651889 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 156617936 61.16% 61.16% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 57255270 22.36% 83.52% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 14082261 5.50% 89.02% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 12088609 4.72% 93.74% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 4189643 1.64% 95.38% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 2964480 1.16% 96.54% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 903129 0.35% 96.89% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 1051661 0.41% 97.30% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 6914549 2.70% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 256067538 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
|
|
system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 77165304 # Number of memory references committed
|
|
system.cpu.commit.loads 56649587 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 12326938 # Number of branches committed
|
|
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 219019985 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 797818 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 1176721 0.53% 0.53% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 133863962 60.47% 61.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 772953 0.35% 61.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 7031501 3.18% 64.53% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 1352943 0.61% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 6914549 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 572164295 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 659850863 # The number of ROB writes
|
|
system.cpu.timesIdled 5930649 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 19653275 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
|
|
system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated
|
|
system.cpu.cpi 2.192174 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 2.192174 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.456168 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.456168 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 451375343 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 234032598 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 3213912 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 2009037 # number of floating regfile writes
|
|
system.cpu.cc_regfile_reads 102846049 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 59805449 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 133386978 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 3852301 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 7156 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 7153 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 132 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 132 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13245 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4286 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 17531 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 419584 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129024 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 548608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 548608 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 8512 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 4433000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 10626750 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 3450631 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 4592 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1628.049417 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 22359876 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 6557 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 3410.077169 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1628.049417 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.794946 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.794946 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 773 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 124 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 810 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 44744077 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 44744077 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 22359876 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 22359876 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 22359876 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 22359876 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 22359876 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 22359876 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 8818 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 8818 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 8818 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 8818 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 8818 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 8818 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 365022750 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 365022750 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 365022750 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 365022750 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 365022750 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 365022750 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 22368694 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 22368694 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 22368694 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 22368694 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 22368694 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 22368694 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000394 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000394 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000394 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000394 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000394 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000394 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41395.185983 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 41395.185983 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 41395.185983 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 41395.185983 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 41395.185983 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 41395.185983 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 701 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 46.733333 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2129 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 2129 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 2129 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 2129 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 2129 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 2129 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6689 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 6689 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 6689 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 6689 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 6689 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 6689 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 269490250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 269490250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 269490250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 269490250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 269490250 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 269490250 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40288.570788 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40288.570788 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40288.570788 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 40288.570788 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40288.570788 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 40288.570788 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 2549.629926 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 3205 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 3824 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.838128 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 1.731773 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2236.346523 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 311.551630 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068248 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.009508 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.077809 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3824 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 895 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2568 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.116699 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 75020 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 75020 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 3162 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 38 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 3200 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 3162 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 44 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 3206 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 3162 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 44 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 3206 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3394 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 429 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 3823 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 131 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 131 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 1533 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 1533 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3394 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 1962 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 5356 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3394 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 1962 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 5356 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 231042500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32071000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 263113500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 103820500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 103820500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 231042500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 135891500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 366934000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 231042500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 135891500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 366934000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 6556 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 467 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 7023 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 132 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 132 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1539 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1539 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 6556 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2006 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 8562 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 6556 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2006 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 8562 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.517694 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.918630 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.544354 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992424 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992424 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996101 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.996101 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.517694 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.978066 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.625555 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.517694 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.978066 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.625555 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68073.806718 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74757.575758 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68823.829453 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67723.744292 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67723.744292 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68073.806718 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69261.722732 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 68508.961912 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68073.806718 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69261.722732 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 68508.961912 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3394 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 429 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 3823 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 131 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 131 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1533 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 1533 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3394 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 1962 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 5356 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3394 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 5356 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 188477000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26778500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 215255500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1310131 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1310131 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 84218500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 84218500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 188477000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 110997000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 299474000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 188477000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 110997000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 299474000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.517694 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.918630 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.544354 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992424 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992424 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996101 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996101 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.517694 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.978066 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.625555 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.517694 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978066 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.625555 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55532.410136 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62420.745921 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56305.388438 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54937.051533 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54937.051533 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55532.410136 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56573.394495 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55913.741598 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55532.410136 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56573.394495 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55913.741598 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 59 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 1435.036669 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 66148000 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 2003 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 33024.463305 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 1435.036669 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.350351 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.350351 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 1944 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 430 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 132302857 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 132302857 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 45633758 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 45633758 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 20514059 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 20514059 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 66147817 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 66147817 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 66147817 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 66147817 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 938 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 938 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1672 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1672 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2610 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2610 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2610 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2610 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 59941301 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 59941301 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 112492631 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 112492631 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 172433932 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 172433932 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 172433932 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 172433932 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 45634696 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 45634696 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 66150427 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 66150427 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 66150427 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 66150427 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63903.305970 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 63903.305970 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67280.281699 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 67280.281699 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 66066.640613 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 66066.640613 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 66066.640613 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 66066.640613 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 322 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 80.500000 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 13 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 13 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 470 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 470 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 472 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 472 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 472 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 472 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 468 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 468 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1670 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1670 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2138 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2138 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2138 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2138 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32985750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 32985750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 108417619 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 108417619 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 141403369 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 141403369 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 141403369 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 141403369 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000081 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000081 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70482.371795 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70482.371795 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64920.729940 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64920.729940 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66138.152011 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66138.152011 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66138.152011 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66138.152011 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|