561 lines
63 KiB
Text
561 lines
63 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.525834 # Number of seconds simulated
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sim_ticks 525834342000 # Number of ticks simulated
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final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 605985 # Simulator instruction rate (inst/s)
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host_op_rate 774729 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1168322503 # Simulator tick rate (ticks/s)
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host_mem_usage 318808 # Number of bytes of host memory used
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host_seconds 450.08 # Real time elapsed on the host
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sim_insts 272739283 # Number of instructions simulated
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sim_ops 348687122 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory
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system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 317545 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 513987 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 831532 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 317545 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 317545 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 317545 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 513987 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 831532 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 831532 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 3976 # Transaction distribution
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system.membus.trans_dist::ReadResp 3976 # Transaction distribution
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system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
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system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 437248 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 191 # Number of system calls
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system.cpu.numCycles 1051668684 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 272739283 # Number of instructions committed
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system.cpu.committedOps 348687122 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
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system.cpu.num_func_calls 12448615 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 18105896 # number of instructions that are conditional controls
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system.cpu.num_int_insts 279584917 # number of integer instructions
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system.cpu.num_fp_insts 114216705 # number of float instructions
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system.cpu.num_int_register_reads 2579483474 # number of times the integer registers were read
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system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
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system.cpu.num_mem_refs 177024356 # number of memory refs
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system.cpu.num_load_insts 94648757 # Number of load instructions
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system.cpu.num_store_insts 82375599 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 1051668684 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.Branches 30563501 # Number of branches fetched
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system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
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system.cpu.op_class::IntAlu 116649413 33.42% 33.42% # Class of executed instruction
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system.cpu.op_class::IntMult 2145905 0.61% 34.03% # Class of executed instruction
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system.cpu.op_class::IntDiv 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::FloatAdd 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::FloatCmp 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::FloatCvt 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::FloatMult 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::FloatDiv 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::FloatSqrt 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdAdd 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdAddAcc 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdAlu 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdCmp 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdCvt 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdMisc 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdMult 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdMultAcc 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdShift 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdShiftAcc 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdSqrt 0 0.00% 34.03% # Class of executed instruction
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system.cpu.op_class::SimdFloatAdd 6594343 1.89% 35.92% # Class of executed instruction
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system.cpu.op_class::SimdFloatAlu 0 0.00% 35.92% # Class of executed instruction
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system.cpu.op_class::SimdFloatCmp 7943502 2.28% 38.20% # Class of executed instruction
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system.cpu.op_class::SimdFloatCvt 3118180 0.89% 39.09% # Class of executed instruction
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system.cpu.op_class::SimdFloatDiv 1563217 0.45% 39.54% # Class of executed instruction
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system.cpu.op_class::SimdFloatMisc 19652356 5.63% 45.17% # Class of executed instruction
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system.cpu.op_class::SimdFloatMult 7136937 2.04% 47.21% # Class of executed instruction
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system.cpu.op_class::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of executed instruction
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system.cpu.op_class::SimdFloatSqrt 175285 0.05% 49.29% # Class of executed instruction
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system.cpu.op_class::MemRead 94648757 27.11% 76.40% # Class of executed instruction
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system.cpu.op_class::MemWrite 82375599 23.60% 100.00% # Class of executed instruction
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system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::total 349065592 # Class of executed instruction
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system.cpu.icache.tags.replacements 13796 # number of replacements
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system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks.
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system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
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system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id
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system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
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system.cpu.icache.tags.tag_accesses 697336303 # Number of tag accesses
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system.cpu.icache.tags.data_accesses 697336303 # Number of data accesses
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system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 348644747 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 348644747 # number of overall hits
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system.cpu.icache.overall_hits::total 348644747 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
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system.cpu.icache.overall_misses::total 15603 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 312417000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 312417000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 312417000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 312417000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 312417000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 312417000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 348660350 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 348660350 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 348660350 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20022.880215 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 20022.880215 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 20022.880215 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 20022.880215 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 176386 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 176386 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 12994 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 12994 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 13249 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2609 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1367 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 3976 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 6832 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135668000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 206752000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 135668000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 355264000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 135668000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 355264000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167211 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.231042 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167211 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2609 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 3976 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104360000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159040000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104360000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 273280000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104360000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 273280000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 1332 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 353296632 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 353296632 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 176619809 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 176619809 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 176619809 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 176619809 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 4478 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 78292000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 78292000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 157288000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 157288000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 235580000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 235580000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 235580000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 235580000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 176624287 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 176624287 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 176624287 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 176624287 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48749.688667 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 48749.688667 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54766.016713 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 54766.016713 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 52608.307280 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 52608.307280 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 998 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 2565553 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 1349056 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|