962 lines
109 KiB
Text
962 lines
109 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.077558 # Number of seconds simulated
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sim_ticks 77558022000 # Number of ticks simulated
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final_tick 77558022000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 184821 # Simulator instruction rate (inst/s)
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host_op_rate 184821 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 38166348 # Simulator tick rate (ticks/s)
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host_mem_usage 274476 # Number of bytes of host memory used
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host_seconds 2032.10 # Real time elapsed on the host
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sim_insts 375574808 # Number of instructions simulated
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sim_ops 375574808 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 221184 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory
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system.physmem.bytes_read::total 476544 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 221184 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 221184 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 3456 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 7446 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 2851852 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3292503 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 6144355 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 2851852 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 2851852 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 2851852 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 3292503 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 6144355 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 7446 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 7446 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 476544 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 476544 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 526 # Per bank write bursts
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system.physmem.perBankRdBursts::1 653 # Per bank write bursts
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system.physmem.perBankRdBursts::2 448 # Per bank write bursts
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system.physmem.perBankRdBursts::3 600 # Per bank write bursts
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system.physmem.perBankRdBursts::4 447 # Per bank write bursts
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system.physmem.perBankRdBursts::5 455 # Per bank write bursts
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system.physmem.perBankRdBursts::6 516 # Per bank write bursts
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system.physmem.perBankRdBursts::7 524 # Per bank write bursts
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system.physmem.perBankRdBursts::8 439 # Per bank write bursts
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system.physmem.perBankRdBursts::9 405 # Per bank write bursts
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system.physmem.perBankRdBursts::10 339 # Per bank write bursts
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system.physmem.perBankRdBursts::11 306 # Per bank write bursts
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system.physmem.perBankRdBursts::12 414 # Per bank write bursts
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system.physmem.perBankRdBursts::13 543 # Per bank write bursts
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system.physmem.perBankRdBursts::14 452 # Per bank write bursts
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system.physmem.perBankRdBursts::15 379 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 77557932500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 7446 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 4325 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 2039 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 758 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 260 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1343 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 351.356664 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 209.733129 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 347.313012 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 424 31.57% 31.57% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 321 23.90% 55.47% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 148 11.02% 66.49% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 81 6.03% 72.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 60 4.47% 76.99% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 47 3.50% 80.49% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 36 2.68% 83.17% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 32 2.38% 85.55% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 194 14.45% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1343 # Bytes accessed per row activation
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system.physmem.totQLat 64732500 # Total ticks spent queuing
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system.physmem.totMemAccLat 204345000 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 37230000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 8693.59 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 27443.59 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 6.14 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 6.14 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.05 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 6090 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 81.79 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 10416053.25 # Average gap between requests
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system.physmem.pageHitRate 81.79 # Row buffer hit rate, read and write combined
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system.physmem.memoryStateTime::IDLE 73756071000 # Time in different power states
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system.physmem.memoryStateTime::REF 2589600000 # Time in different power states
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::ACT 1205652750 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.membus.throughput 6144355 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 4314 # Transaction distribution
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system.membus.trans_dist::ReadResp 4314 # Transaction distribution
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system.membus.trans_dist::ReadExReq 3132 # Transaction distribution
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system.membus.trans_dist::ReadExResp 3132 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14892 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 14892 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476544 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 476544 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 476544 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 9331000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.respLayer1.occupancy 69621500 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.branchPred.lookups 50345417 # Number of BP lookups
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system.cpu.branchPred.condPredicted 29291104 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 1215969 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 26826828 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 23310375 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 86.892028 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 9011574 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 1048 # Number of incorrect RAS predictions.
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 101817662 # DTB read hits
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system.cpu.dtb.read_misses 78218 # DTB read misses
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system.cpu.dtb.read_acv 48604 # DTB read access violations
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system.cpu.dtb.read_accesses 101895880 # DTB read accesses
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system.cpu.dtb.write_hits 78432784 # DTB write hits
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system.cpu.dtb.write_misses 1485 # DTB write misses
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system.cpu.dtb.write_acv 3 # DTB write access violations
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system.cpu.dtb.write_accesses 78434269 # DTB write accesses
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system.cpu.dtb.data_hits 180250446 # DTB hits
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system.cpu.dtb.data_misses 79703 # DTB misses
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system.cpu.dtb.data_acv 48607 # DTB access violations
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system.cpu.dtb.data_accesses 180330149 # DTB accesses
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system.cpu.itb.fetch_hits 50303452 # ITB hits
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system.cpu.itb.fetch_misses 374 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 50303826 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 215 # Number of system calls
|
|
system.cpu.numCycles 155116046 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 51199541 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 449368258 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 50345417 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 32321949 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 78906536 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 6198249 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.BlockedCycles 19757533 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 186 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 10530 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 50303452 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 417357 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 154817464 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.902568 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.324801 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 75910928 49.03% 49.03% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 4292900 2.77% 51.81% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 6887952 4.45% 56.25% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 5378426 3.47% 59.73% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 11777021 7.61% 67.34% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 7819850 5.05% 72.39% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 5605225 3.62% 76.01% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 1835804 1.19% 77.19% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 35309358 22.81% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 154817464 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.324566 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 2.896981 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 56574106 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 15095997 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 74265148 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 3943304 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 4938909 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 9501741 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 4271 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 445384778 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 12171 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 4938909 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 59715078 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 4876409 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 419715 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 75168099 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 9699254 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 440873304 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 26337 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 8019570 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RenamedOperands 287561386 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 579637001 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 414043720 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 165593280 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 28029057 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 36796 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 273 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 27775978 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 104708247 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 80640808 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 8927201 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 6403621 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 408496151 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 259 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 401987429 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 970780 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 32786458 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 15509808 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 154817464 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 2.596525 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.995719 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 28475792 18.39% 18.39% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 25868593 16.71% 35.10% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 25622739 16.55% 51.65% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 24250418 15.66% 67.32% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 21294797 13.75% 81.07% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 15492171 10.01% 91.08% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 8526240 5.51% 96.59% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 3969091 2.56% 99.15% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 1317623 0.85% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 154817464 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 33961 0.29% 0.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 60734 0.51% 0.80% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 4893 0.04% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 5332 0.05% 0.89% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 1940982 16.38% 17.27% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 1755182 14.82% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 5081532 42.89% 74.98% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 2964138 25.02% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 155819959 38.76% 38.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 2126233 0.53% 39.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 32858833 8.17% 47.47% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 7513495 1.87% 49.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 2793143 0.69% 50.04% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 16555819 4.12% 54.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 1584570 0.39% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 103403919 25.72% 80.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 79297877 19.73% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 401987429 # Type of FU issued
|
|
system.cpu.iq.rate 2.591527 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 11846754 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.029470 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 634443309 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 260407475 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 234772020 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 337166547 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 180924376 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 161447715 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 241509351 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 172291251 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 15019191 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 9953760 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 111699 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 48994 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 7120079 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 260856 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 3918 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 4938909 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 2515248 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 368703 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 433326930 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 121866 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 104708247 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 80640808 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 259 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 84 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 84 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 48994 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 963874 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 408153 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 1372027 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 398387733 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 101944518 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 3599696 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 24830520 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 180378816 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 46578472 # Number of branches executed
|
|
system.cpu.iew.exec_stores 78434298 # Number of stores executed
|
|
system.cpu.iew.exec_rate 2.568321 # Inst execution rate
|
|
system.cpu.iew.wb_sent 396855480 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 396219735 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 193571599 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 271152784 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 2.554344 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.713884 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 34693909 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 1211780 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 149878555 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 2.659917 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.995453 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 55522565 37.05% 37.05% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 22544256 15.04% 52.09% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 13057076 8.71% 60.80% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 11473348 7.66% 68.45% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 8182798 5.46% 73.91% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 5442795 3.63% 77.54% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 5157024 3.44% 80.99% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 3290724 2.20% 83.18% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 25207969 16.82% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 149878555 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 398664583 # Number of instructions committed
|
|
system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 168275216 # Number of memory references committed
|
|
system.cpu.commit.loads 94754487 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 44587533 # Number of branches committed
|
|
system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 316365839 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 145805186 36.57% 42.37% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 2124322 0.53% 42.91% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 42.91% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 31467419 7.89% 50.80% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 94754487 23.77% 81.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 25207969 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 558026101 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 871664409 # The number of ROB writes
|
|
system.cpu.timesIdled 3592 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 298582 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 375574808 # Number of Instructions Simulated
|
|
system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.413010 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.413010 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 2.421251 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 2.421251 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 398150942 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 170167166 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 156627293 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 104100522 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 7339228 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 5048 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 5048 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 655 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 3191 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 3191 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8126 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9007 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 17133 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260032 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309184 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 569216 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 569216 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 5102000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 6747750 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 6703500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 2136 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1830.591331 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 50297811 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 4063 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 12379.476003 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1830.591331 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.893843 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.893843 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 331 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1340 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 100610967 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 100610967 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 50297811 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 50297811 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 50297811 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 50297811 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 50297811 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 50297811 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 5641 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 5641 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 5641 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 5641 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 5641 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 5641 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 335074000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 335074000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 335074000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 335074000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 335074000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 335074000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 50303452 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 50303452 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 50303452 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 50303452 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 50303452 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 50303452 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000112 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000112 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000112 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000112 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000112 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000112 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59399.751817 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 59399.751817 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 59399.751817 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 59399.751817 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 59399.751817 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 59399.751817 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 446 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 49.555556 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1578 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 1578 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 1578 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 1578 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 1578 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 1578 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4063 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 4063 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 4063 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 4063 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 4063 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 4063 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249433250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 249433250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249433250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 249433250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249433250 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 249433250 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61391.397982 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61391.397982 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61391.397982 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 61391.397982 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61391.397982 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 61391.397982 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 4004.954677 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 821 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 4850 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.169278 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 371.321858 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2975.631846 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 658.000972 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.011332 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090809 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.020081 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.122222 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4850 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 573 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4031 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148010 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 79193 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 79193 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 607 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 127 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 734 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 655 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 655 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 59 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 59 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 607 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 186 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 793 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 607 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 186 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 793 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3456 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 858 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 4314 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 3132 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 3132 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3456 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 3990 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 7446 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3456 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 3990 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 7446 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239290500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 65195250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 304485750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 229768250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 229768250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 239290500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 294963500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 534254000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 239290500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 294963500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 534254000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4063 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 985 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 5048 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 655 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 655 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3191 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 3191 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 4063 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 4176 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 8239 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 4063 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 4176 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 8239 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.850603 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.871066 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.854596 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981510 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981510 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.850603 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955460 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.903750 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.850603 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955460 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.903750 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69239.149306 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75985.139860 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70580.841446 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73361.510217 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73361.510217 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69239.149306 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73925.689223 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 71750.470051 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69239.149306 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73925.689223 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 71750.470051 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3456 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 858 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4314 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3132 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 3132 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3456 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 3990 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 7446 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3456 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 3990 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 7446 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195490000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54612750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250102750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 191098750 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 191098750 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195490000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 245711500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 441201500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195490000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 245711500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 441201500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.850603 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871066 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.854596 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981510 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981510 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.850603 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955460 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.903750 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.850603 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955460 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.903750 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56565.393519 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63651.223776 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57974.675475 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61014.926564 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61014.926564 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56565.393519 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61581.829574 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59253.491808 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56565.393519 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61581.829574 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59253.491808 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 774 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 3296.550770 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 160033276 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 4176 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 38322.144636 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 3296.550770 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.804822 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.804822 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 3402 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3119 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.830566 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 320114012 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 320114012 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 86532394 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 86532394 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 73500878 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 73500878 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 160033272 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 160033272 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 160033272 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 160033272 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1791 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1791 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 19851 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 19851 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 21642 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 21642 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 21642 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 21642 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 112278750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 112278750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1112532070 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 1112532070 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 1224810820 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 1224810820 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 1224810820 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 1224810820 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 86534185 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 86534185 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 160054914 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 160054914 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 160054914 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 160054914 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000270 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000270 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000135 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62690.536013 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 62690.536013 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56044.132286 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 56044.132286 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56594.160429 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 56594.160429 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56594.160429 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 56594.160429 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 40644 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 681 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.682819 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 655 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 655 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 806 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 806 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16660 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 16660 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 17466 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 17466 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 17466 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 17466 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 985 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 985 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3191 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 3191 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 4176 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 4176 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 4176 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 4176 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67500250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 67500250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 233649750 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 233649750 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 301150000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 301150000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 301150000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 301150000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68528.172589 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68528.172589 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73221.482294 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73221.482294 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72114.463602 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72114.463602 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72114.463602 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72114.463602 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
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