gem5/src
Abdul Mutaal Ahmad 7cb0c7bd65 mem: different HMC configuration
In this new hmc configuration we have used the existing components in gem5
mainly [SerialLink] [NoncoherentXbar]& [DRAMCtrl] to define 3 different
architecture for HMC.

Highlights

1- It explores 3 different HMC architectures

2- It creates 4-HMC crossbars and attaches 16 vault controllers with it.
This  will connect vaults to serial links

3- From the previous version, HMCController with round robin funtionality
is being removed and all the serial links are being accessible directly
from user ports

4- Latency incorporated by HMCController (in previous version) is being
added to SerialLink

Committed by Jason Lowe-Power <jason@lowepower.com>
2016-07-01 09:45:21 -05:00
..
arch arm: Mark uninitialized new TLB entries as not valid 2016-06-20 15:51:31 +01:00
base base: Fix multiple names to one address bug in SymbolTable 2016-06-20 14:39:48 +01:00
cpu mem: Resolve TrafficGen trace relative to the config 2016-06-20 14:49:37 +01:00
dev dist, dev: Fixed the packet ordering in etherswitch 2016-06-08 09:12:41 -05:00
doc sim: Adding support for power models 2016-06-06 17:16:44 +01:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
gpu-compute gpu-compute: parametrize Wavefront size 2016-06-09 11:24:55 -04:00
kern kern, arm: Dump dmesg on kernel panic/oops 2016-06-20 14:39:49 +01:00
mem mem: different HMC configuration 2016-07-01 09:45:21 -05:00
proto cpu: Support virtual addr in elastic traces 2015-12-07 16:42:16 -06:00
python power: Allow voltage to be configured via cmd line 2016-05-27 16:54:59 +01:00
sim scons: Track swig packages when loading embedded swig code 2016-06-28 03:50:00 -04:00
unittest style: remove trailing whitespace 2016-02-06 17:21:18 -08:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript scons: Track swig packages when loading embedded swig code 2016-06-28 03:50:00 -04:00