gem5/src/arch/power/types.hh
Andreas Hansson b6aa6d55eb clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6
This patch addresses a number of minor issues that cause problems when
compiling with clang >= 3.0 and gcc >= 4.6. Most importantly, it
avoids using the deprecated ext/hash_map and instead uses
unordered_map (and similarly so for the hash_set). To make use of the
new STL containers, g++ and clang has to be invoked with "-std=c++0x",
and this is now added for all gcc versions >= 4.6, and for clang >=
3.0. For gcc >= 4.3 and <= 4.5 and clang <= 3.0 we use the tr1
unordered_map to avoid the deprecation warning.

The addition of c++0x in turn causes a few problems, as the
compiler is more stringent and adds a number of new warnings. Below,
the most important issues are enumerated:

1) the use of namespaces is more strict, e.g. for isnan, and all
   headers opening the entire namespace std are now fixed.

2) another other issue caused by the more stringent compiler is the
   narrowing of the embedded python, which used to be a char array,
   and is now unsigned char since there were values larger than 128.

3) a particularly odd issue that arose with the new c++0x behaviour is
   found in range.hh, where the operator< causes gcc to complain about
   the template type parsing (the "<" is interpreted as the beginning
   of a template argument), and the problem seems to be related to the
   begin/end members introduced for the range-type iteration, which is
   a new feature in c++11.

As a minor update, this patch also fixes the build flags for the clang
debug target that used to be shared with gcc and incorrectly use
"-ggdb".
2012-04-14 05:43:31 -04:00

103 lines
3.1 KiB
C++

/*
* Copyright (c) 2009 The University of Edinburgh
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Timothy M. Jones
*/
#ifndef __ARCH_POWER_TYPES_HH__
#define __ARCH_POWER_TYPES_HH__
#include "arch/generic/types.hh"
#include "base/bitunion.hh"
#include "base/hashmap.hh"
#include "base/types.hh"
namespace PowerISA
{
typedef uint32_t MachInst;
BitUnion32(ExtMachInst)
// Registers
Bitfield<25, 21> rs;
Bitfield<20, 16> ra;
// Shifts and masks
Bitfield<15, 11> sh;
Bitfield<10, 6> mb;
Bitfield< 5, 1> me;
// Immediate fields
Bitfield<15, 0> si;
Bitfield<15, 0> d;
// Special purpose register identifier
Bitfield<20, 11> spr;
Bitfield<25, 2> li;
Bitfield<1> aa;
Bitfield<25, 23> bf;
Bitfield<15, 2> bd;
Bitfield<25, 21> bo;
Bitfield<20, 16> bi;
Bitfield<20, 18> bfa;
// Record bits
Bitfield<0> rc31;
Bitfield<10> oe;
// Condition register fields
Bitfield<25, 21> bt;
Bitfield<20, 16> ba;
Bitfield<15, 11> bb;
// FXM field for mtcrf instruction
Bitfield<19, 12> fxm;
EndBitUnion(ExtMachInst)
typedef GenericISA::SimplePCState<MachInst> PCState;
// typedef uint64_t LargestRead;
// // Need to use 64 bits to make sure that read requests get handled properly
// typedef int RegContextParam;
// typedef int RegContextVal;
} // PowerISA namespace
__hash_namespace_begin
template<>
struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
size_t operator()(const PowerISA::ExtMachInst &emi) const {
return hash<uint32_t>::operator()((uint32_t)emi);
};
};
__hash_namespace_end
#endif // __ARCH_POWER_TYPES_HH__