227 lines
6.2 KiB
C++
227 lines
6.2 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Ron Dreslinski
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* Ali Saidi
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*/
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/**
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* @file
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* Definitions of page table.
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*/
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#include <string>
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#include <map>
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#include <fstream>
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#include "arch/faults.hh"
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#include "base/bitfield.hh"
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#include "base/intmath.hh"
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#include "base/trace.hh"
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#include "config/the_isa.hh"
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#include "mem/page_table.hh"
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#include "sim/process.hh"
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#include "sim/sim_object.hh"
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#include "sim/system.hh"
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using namespace std;
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using namespace TheISA;
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PageTable::PageTable(Process *_process, Addr _pageSize)
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: pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
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process(_process)
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{
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assert(isPowerOf2(pageSize));
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pTableCache[0].vaddr = 0;
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pTableCache[1].vaddr = 0;
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pTableCache[2].vaddr = 0;
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}
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PageTable::~PageTable()
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{
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}
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void
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PageTable::allocate(Addr vaddr, int64_t size)
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{
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// starting address must be page aligned
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assert(pageOffset(vaddr) == 0);
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DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
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for (; size > 0; size -= pageSize, vaddr += pageSize) {
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PTableItr iter = pTable.find(vaddr);
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if (iter != pTable.end()) {
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// already mapped
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fatal("PageTable::allocate: address 0x%x already mapped",
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vaddr);
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}
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pTable[vaddr] = TheISA::TlbEntry(process->M5_pid, vaddr,
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process->system->new_page());
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updateCache(vaddr, pTable[vaddr]);
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}
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}
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void
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PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
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{
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assert(pageOffset(vaddr) == 0);
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assert(pageOffset(new_vaddr) == 0);
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DPRINTF(MMU, "moving pages from vaddr %08p to %08p, size = %d\n", vaddr,
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new_vaddr, size);
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for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr += pageSize) {
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PTableItr iter = pTable.find(vaddr);
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assert(iter != pTable.end());
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pTable[new_vaddr] = pTable[vaddr];
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pTable.erase(vaddr);
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pTable[new_vaddr].updateVaddr(new_vaddr);
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updateCache(new_vaddr, pTable[new_vaddr]);
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}
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}
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void
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PageTable::deallocate(Addr vaddr, int64_t size)
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{
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assert(pageOffset(vaddr) == 0);
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DPRINTF(MMU, "Deallocating page: %#x-%#x\n", vaddr, vaddr+ size);
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for (; size > 0; size -= pageSize, vaddr += pageSize) {
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PTableItr iter = pTable.find(vaddr);
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assert(iter != pTable.end());
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pTable.erase(vaddr);
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}
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}
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bool
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PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
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{
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Addr page_addr = pageAlign(vaddr);
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if (pTableCache[0].vaddr == page_addr) {
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entry = pTableCache[0].entry;
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return true;
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}
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if (pTableCache[1].vaddr == page_addr) {
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entry = pTableCache[1].entry;
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return true;
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}
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if (pTableCache[2].vaddr == page_addr) {
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entry = pTableCache[2].entry;
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return true;
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}
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PTableItr iter = pTable.find(page_addr);
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if (iter == pTable.end()) {
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return false;
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}
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updateCache(page_addr, iter->second);
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entry = iter->second;
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return true;
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}
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bool
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PageTable::translate(Addr vaddr, Addr &paddr)
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{
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TheISA::TlbEntry entry;
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if (!lookup(vaddr, entry)) {
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DPRINTF(MMU, "Couldn't Translate: %#x\n", vaddr);
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return false;
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}
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paddr = pageOffset(vaddr) + entry.pageStart();
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DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr);
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return true;
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}
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Fault
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PageTable::translate(RequestPtr req)
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{
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Addr paddr;
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assert(pageAlign(req->getVaddr() + req->getSize() - 1)
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== pageAlign(req->getVaddr()));
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if (!translate(req->getVaddr(), paddr)) {
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return Fault(new GenericPageTableFault(req->getVaddr()));
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}
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req->setPaddr(paddr);
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if ((paddr & (pageSize - 1)) + req->getSize() > pageSize) {
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panic("Request spans page boundaries!\n");
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return NoFault;
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}
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return NoFault;
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}
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void
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PageTable::serialize(std::ostream &os)
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{
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paramOut(os, "ptable.size", pTable.size());
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PTable::size_type count = 0;
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PTableItr iter = pTable.begin();
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PTableItr end = pTable.end();
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while (iter != end) {
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os << "\n[" << csprintf("%s.Entry%d", process->name(), count) << "]\n";
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paramOut(os, "vaddr", iter->first);
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iter->second.serialize(os);
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++iter;
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++count;
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}
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assert(count == pTable.size());
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}
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void
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PageTable::unserialize(Checkpoint *cp, const std::string §ion)
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{
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int i = 0, count;
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paramIn(cp, section, "ptable.size", count);
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Addr vaddr;
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TheISA::TlbEntry *entry;
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pTable.clear();
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while(i < count) {
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paramIn(cp, csprintf("%s.Entry%d", process->name(), i), "vaddr", vaddr);
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entry = new TheISA::TlbEntry();
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entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i));
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pTable[vaddr] = *entry;
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++i;
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}
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}
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