81a735a716
Time to make the ide device work
arch/alpha/system.cc:
write the machine type and rev in the correct place
cpu/simple/cpu.cc:
reset the packet structure every time it's reused... wow the
simple cpu code for talking to memory is getting horrible.
dev/alpha_console.cc:
move the setAlphaAccess to startup() to make sure that the console
binary is loaded
dev/tsunami_cchip.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
fix a couple of bugs injected in the newmem fixes
mem/bus.cc:
More verbose bus tracing
mem/packet.hh:
Add a constructor to packet to set the result to unknown and a reset
method in the case it's being reused
mem/vport.hh:
don't need are own read/write methods since the base functional port
ones call writeBlob readBlob which do the translation for us
--HG--
extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
140 lines
4.1 KiB
C++
140 lines
4.1 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file Definition of a bus object.
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*/
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#include "base/trace.hh"
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#include "mem/bus.hh"
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#include "sim/builder.hh"
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/** Function called by the port when the bus is recieving a Timing
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* transaction.*/
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bool
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Bus::recvTiming(Packet &pkt, int id)
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{
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panic("I need to be implemented, but not right now.");
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}
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Port *
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Bus::findPort(Addr addr, int id)
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{
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/* An interval tree would be a better way to do this. --ali. */
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int dest_id = -1;
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int i = 0;
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bool found = false;
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while (i < portList.size() && !found)
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{
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if (portList[i].range == addr) {
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dest_id = portList[i].portId;
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found = true;
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DPRINTF(Bus, "Found Addr: %llx on device %d\n", addr, dest_id);
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}
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i++;
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}
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if (dest_id == -1)
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panic("Unable to find destination for addr: %llx", addr);
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// we shouldn't be sending this back to where it came from
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assert(dest_id != id);
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return interfaces[dest_id];
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}
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/** Function called by the port when the bus is recieving a Atomic
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* transaction.*/
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Tick
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Bus::recvAtomic(Packet &pkt, int id)
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{
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return findPort(pkt.addr, id)->sendAtomic(pkt);
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}
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/** Function called by the port when the bus is recieving a Functional
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* transaction.*/
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void
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Bus::recvFunctional(Packet &pkt, int id)
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{
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findPort(pkt.addr, id)->sendFunctional(pkt);
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}
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/** Function called by the port when the bus is recieving a status change.*/
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void
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Bus::recvStatusChange(Port::Status status, int id)
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{
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assert(status == Port::RangeChange &&
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"The other statuses need to be implemented.");
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assert(id < interfaces.size() && id >= 0);
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Port *port = interfaces[id];
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AddrRangeList ranges;
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AddrRangeList snoops;
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port->getPeerAddressRanges(ranges, snoops);
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// not dealing with snooping yet either
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assert(snoops.size() == 0);
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// or multiple ranges
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assert(ranges.size() == 1);
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DevMap dm;
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dm.portId = id;
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dm.range = ranges.front();
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DPRINTF(MMU, "Adding range %llx - %llx for id %d\n", dm.range.start,
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dm.range.end, id);
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portList.push_back(dm);
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DPRINTF(MMU, "port list has %d entries\n", portList.size());
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}
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void
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Bus::BusPort::addressRanges(AddrRangeList &resp, AddrRangeList &snoop)
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{
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panic("I'm not implemented.\n");
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
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Param<int> bus_id;
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END_DECLARE_SIM_OBJECT_PARAMS(Bus)
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BEGIN_INIT_SIM_OBJECT_PARAMS(Bus)
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INIT_PARAM(bus_id, "junk bus id")
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END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
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CREATE_SIM_OBJECT(Bus)
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{
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return new Bus(getInstanceName());
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}
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REGISTER_SIM_OBJECT("Bus", Bus)
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