043709fdfa
Enables the CheckerCPU to be selected at runtime with the --checker option from the configs/example/fs.py and configs/example/se.py configuration files. Also merges with the SE/FS changes.
215 lines
7 KiB
C++
215 lines
7 KiB
C++
/*
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* Copyright (c) 2010-2011 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#include "base/cp_annotate.hh"
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#include "cpu/o3/dyn_inst.hh"
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#include "sim/full_system.hh"
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template <class Impl>
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BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
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StaticInstPtr macroop,
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TheISA::PCState pc, TheISA::PCState predPC,
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InstSeqNum seq_num, O3CPU *cpu)
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: BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
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{
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initVars();
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}
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template <class Impl>
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BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr _staticInst,
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StaticInstPtr _macroop)
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: BaseDynInst<Impl>(_staticInst, _macroop)
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{
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initVars();
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}
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template <class Impl>
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void
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BaseO3DynInst<Impl>::initVars()
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{
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// Make sure to have the renamed register entries set to the same
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// as the normal register entries. It will allow the IQ to work
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// without any modifications.
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for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
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this->_destRegIdx[i] = this->staticInst->destRegIdx(i);
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}
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for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
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this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
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this->_readySrcRegIdx[i] = 0;
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}
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_numDestMiscRegs = 0;
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#if TRACING_ON
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fetchTick = 0;
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decodeTick = 0;
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renameTick = 0;
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dispatchTick = 0;
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issueTick = 0;
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completeTick = 0;
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#endif
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}
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template <class Impl>
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Fault
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BaseO3DynInst<Impl>::execute()
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{
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// @todo: Pretty convoluted way to avoid squashing from happening
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// when using the TC during an instruction's execution
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// (specifically for instructions that have side-effects that use
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// the TC). Fix this.
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bool in_syscall = this->thread->inSyscall;
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this->thread->inSyscall = true;
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this->fault = this->staticInst->execute(this, this->traceData);
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this->thread->inSyscall = in_syscall;
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return this->fault;
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}
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template <class Impl>
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Fault
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BaseO3DynInst<Impl>::initiateAcc()
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{
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// @todo: Pretty convoluted way to avoid squashing from happening
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// when using the TC during an instruction's execution
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// (specifically for instructions that have side-effects that use
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// the TC). Fix this.
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bool in_syscall = this->thread->inSyscall;
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this->thread->inSyscall = true;
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this->fault = this->staticInst->initiateAcc(this, this->traceData);
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this->thread->inSyscall = in_syscall;
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return this->fault;
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}
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template <class Impl>
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Fault
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BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
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{
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// @todo: Pretty convoluted way to avoid squashing from happening
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// when using the TC during an instruction's execution
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// (specifically for instructions that have side-effects that use
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// the TC). Fix this.
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bool in_syscall = this->thread->inSyscall;
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this->thread->inSyscall = true;
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if (this->cpu->checker) {
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if (this->isStoreConditional()) {
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this->reqToVerify->setExtraData(pkt->req->getExtraData());
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}
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}
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this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
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this->thread->inSyscall = in_syscall;
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return this->fault;
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}
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template <class Impl>
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Fault
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BaseO3DynInst<Impl>::hwrei()
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{
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#if THE_ISA == ALPHA_ISA
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// Can only do a hwrei when in pal mode.
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if (!(this->instAddr() & 0x3))
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return new AlphaISA::UnimplementedOpcodeFault;
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// Set the next PC based on the value of the EXC_ADDR IPR.
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AlphaISA::PCState pc = this->pcState();
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pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
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this->threadNumber));
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this->pcState(pc);
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if (CPA::available()) {
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ThreadContext *tc = this->cpu->tcBase(this->threadNumber);
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CPA::cpa()->swAutoBegin(tc, this->nextInstAddr());
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}
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// Tell CPU to clear any state it needs to if a hwrei is taken.
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this->cpu->hwrei(this->threadNumber);
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#else
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#endif
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// FIXME: XXX check for interrupts? XXX
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return NoFault;
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}
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template <class Impl>
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void
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BaseO3DynInst<Impl>::trap(Fault fault)
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{
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this->cpu->trap(fault, this->threadNumber, this->staticInst);
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}
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template <class Impl>
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bool
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BaseO3DynInst<Impl>::simPalCheck(int palFunc)
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{
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#if THE_ISA != ALPHA_ISA
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panic("simPalCheck called, but PAL only exists in Alpha!\n");
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#endif
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return this->cpu->simPalCheck(palFunc, this->threadNumber);
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}
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template <class Impl>
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void
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BaseO3DynInst<Impl>::syscall(int64_t callnum)
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{
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if (FullSystem)
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panic("Syscall emulation isn't available in FS mode.\n");
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// HACK: check CPU's nextPC before and after syscall. If it
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// changes, update this instruction's nextPC because the syscall
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// must have changed the nextPC.
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TheISA::PCState curPC = this->cpu->pcState(this->threadNumber);
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this->cpu->syscall(callnum, this->threadNumber);
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TheISA::PCState newPC = this->cpu->pcState(this->threadNumber);
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if (!(curPC == newPC)) {
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this->pcState(newPC);
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}
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}
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