They are now accessed by calling readMiscReg()/setMiscReg() on the XC. Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future). arch/alpha/alpha_memory.cc: Change accesses to IPR to go through the XC. arch/alpha/ev5.cc: Change accesses for IPRs to go through the misc regs. arch/alpha/isa/decoder.isa: Change accesses to IPRs to go through the misc regs. readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect(). arch/alpha/isa/fp.isa: Change accesses to IPRs and Fpcr to go through the misc regs. arch/alpha/isa/main.isa: Add support for all misc regs being accessed through readMiscReg() and setMiscReg(). Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index. arch/alpha/isa_traits.hh: Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs. Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect. The latter are basically the original read/write IPR functions, while the former are normal reads/writes. The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs. arch/alpha/stacktrace.cc: cpu/simple/cpu.cc: dev/sinic.cc: Change accesses to the IPRs to go through the XC. arch/alpha/vtophys.cc: Change access to the IPR to go through the XC. arch/isa_parser.py: Change generation of code for control registers to use the readMiscReg and setMiscReg functions. base/remote_gdb.cc: Change accesses to the IPR to go through the XC. cpu/exec_context.hh: Use the miscRegs to access the lock addr, lock flag, and other misc registers. cpu/o3/alpha_cpu.hh: cpu/simple/cpu.hh: Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions. cpu/o3/alpha_cpu_impl.hh: Change accesses to the IPRs to go through the miscRegs. For now comment out some of the accesses to the misc regs until the proxy exec context is completed. cpu/o3/alpha_dyn_inst.hh: Change accesses to misc regs to use readMiscReg and setMiscReg. cpu/o3/alpha_dyn_inst_impl.hh: Remove old misc reg accessors. cpu/o3/cpu.cc: Comment out old misc reg accesses until the proxy exec context is completed. cpu/o3/cpu.hh: Change accesses to the misc regs. cpu/o3/regfile.hh: Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg. They are dummy functions for now until the proxy exec context is completed. kern/kernel_stats.cc: kern/system_events.cc: Have accesses to the IPRs go through the XC. kern/tru64/tru64.hh: Have accesses to the misc regs use the new access methods. --HG-- extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76
360 lines
9.7 KiB
C++
360 lines
9.7 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
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#define __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
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#include "base/statistics.hh"
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#include "config/full_system.hh"
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#include "cpu/base.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/pc_event.hh"
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#include "cpu/sampler/sampler.hh"
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#include "cpu/static_inst.hh"
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#include "sim/eventq.hh"
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// forward declarations
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#if FULL_SYSTEM
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class Processor;
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class AlphaITB;
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class AlphaDTB;
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class PhysicalMemory;
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class RemoteGDB;
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class GDBListener;
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#else
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class Process;
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#endif // FULL_SYSTEM
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class MemInterface;
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class Checkpoint;
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namespace Trace {
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class InstRecord;
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}
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class SimpleCPU : public BaseCPU
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{
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protected:
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typedef TheISA::MachInst MachInst;
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typedef TheISA::MiscReg MiscReg;
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public:
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// main simulation loop (one cycle)
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void tick();
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virtual void init();
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private:
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struct TickEvent : public Event
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{
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SimpleCPU *cpu;
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int width;
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TickEvent(SimpleCPU *c, int w);
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void process();
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const char *description();
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};
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TickEvent tickEvent;
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/// Schedule tick event, regardless of its current state.
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void scheduleTickEvent(int numCycles)
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{
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if (tickEvent.squashed())
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tickEvent.reschedule(curTick + cycles(numCycles));
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else if (!tickEvent.scheduled())
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tickEvent.schedule(curTick + cycles(numCycles));
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}
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/// Unschedule tick event, regardless of its current state.
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void unscheduleTickEvent()
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{
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if (tickEvent.scheduled())
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tickEvent.squash();
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}
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private:
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Trace::InstRecord *traceData;
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public:
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//
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enum Status {
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Running,
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Idle,
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IcacheMissStall,
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IcacheMissComplete,
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DcacheMissStall,
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DcacheMissSwitch,
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SwitchedOut
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};
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private:
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Status _status;
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public:
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void post_interrupt(int int_num, int index);
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void zero_fill_64(Addr addr) {
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static int warned = 0;
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if (!warned) {
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warn ("WH64 is not implemented");
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warned = 1;
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}
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};
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public:
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struct Params : public BaseCPU::Params
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{
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MemInterface *icache_interface;
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MemInterface *dcache_interface;
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int width;
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#if FULL_SYSTEM
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AlphaITB *itb;
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AlphaDTB *dtb;
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FunctionalMemory *mem;
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#else
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Process *process;
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#endif
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};
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SimpleCPU(Params *params);
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virtual ~SimpleCPU();
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public:
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// execution context
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ExecContext *xc;
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void switchOut(Sampler *s);
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void takeOverFrom(BaseCPU *oldCPU);
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#if FULL_SYSTEM
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Addr dbg_vtophys(Addr addr);
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bool interval_stats;
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#endif
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// L1 instruction cache
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MemInterface *icacheInterface;
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// L1 data cache
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MemInterface *dcacheInterface;
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// current instruction
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MachInst inst;
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// Refcounted pointer to the one memory request.
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MemReqPtr memReq;
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// Pointer to the sampler that is telling us to switchover.
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// Used to signal the completion of the pipe drain and schedule
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// the next switchover
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Sampler *sampler;
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StaticInstPtr curStaticInst;
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class CacheCompletionEvent : public Event
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{
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private:
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SimpleCPU *cpu;
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public:
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CacheCompletionEvent(SimpleCPU *_cpu);
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virtual void process();
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virtual const char *description();
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};
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CacheCompletionEvent cacheCompletionEvent;
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Status status() const { return _status; }
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virtual void activateContext(int thread_num, int delay);
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virtual void suspendContext(int thread_num);
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virtual void deallocateContext(int thread_num);
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virtual void haltContext(int thread_num);
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// statistics
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virtual void regStats();
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virtual void resetStats();
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// number of simulated instructions
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Counter numInst;
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Counter startNumInst;
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Stats::Scalar<> numInsts;
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virtual Counter totalInstructions() const
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{
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return numInst - startNumInst;
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}
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// number of simulated memory references
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Stats::Scalar<> numMemRefs;
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// number of simulated loads
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Counter numLoad;
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Counter startNumLoad;
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// number of idle cycles
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Stats::Average<> notIdleFraction;
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Stats::Formula idleFraction;
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// number of cycles stalled for I-cache misses
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Stats::Scalar<> icacheStallCycles;
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Counter lastIcacheStall;
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// number of cycles stalled for D-cache misses
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Stats::Scalar<> dcacheStallCycles;
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Counter lastDcacheStall;
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void processCacheCompletion();
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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template <class T>
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Fault read(Addr addr, T &data, unsigned flags);
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template <class T>
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Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
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// These functions are only used in CPU models that split
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// effective address computation from the actual memory access.
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void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
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Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
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void prefetch(Addr addr, unsigned flags)
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{
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// need to do this...
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}
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void writeHint(Addr addr, int size, unsigned flags)
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{
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// need to do this...
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}
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Fault copySrcTranslate(Addr src);
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Fault copy(Addr dest);
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// The register accessor methods provide the index of the
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// instruction's operand (e.g., 0 or 1), not the architectural
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// register index, to simplify the implementation of register
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// renaming. We find the architectural register index by indexing
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// into the instruction's own operand index table. Note that a
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// raw pointer to the StaticInst is provided instead of a
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// ref-counted StaticInstPtr to redice overhead. This is fine as
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// long as these methods don't copy the pointer into any long-term
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// storage (which is pretty hard to imagine they would have reason
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// to do).
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uint64_t readIntReg(const StaticInst *si, int idx)
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{
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return xc->readIntReg(si->srcRegIdx(idx));
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}
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float readFloatRegSingle(const StaticInst *si, int idx)
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
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return xc->readFloatRegSingle(reg_idx);
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}
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double readFloatRegDouble(const StaticInst *si, int idx)
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
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return xc->readFloatRegDouble(reg_idx);
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}
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uint64_t readFloatRegInt(const StaticInst *si, int idx)
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
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return xc->readFloatRegInt(reg_idx);
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}
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void setIntReg(const StaticInst *si, int idx, uint64_t val)
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{
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xc->setIntReg(si->destRegIdx(idx), val);
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}
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void setFloatRegSingle(const StaticInst *si, int idx, float val)
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
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xc->setFloatRegSingle(reg_idx, val);
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}
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void setFloatRegDouble(const StaticInst *si, int idx, double val)
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
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xc->setFloatRegDouble(reg_idx, val);
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}
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void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
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xc->setFloatRegInt(reg_idx, val);
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}
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uint64_t readPC() { return xc->readPC(); }
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void setNextPC(uint64_t val) { xc->setNextPC(val); }
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MiscReg readMiscReg(int misc_reg)
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{
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return xc->readMiscReg(misc_reg);
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}
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MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
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{
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return xc->readMiscRegWithEffect(misc_reg, fault);
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}
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Fault setMiscReg(int misc_reg, const MiscReg &val)
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{
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return xc->setMiscReg(misc_reg, val);
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}
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Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
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{
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return xc->setMiscRegWithEffect(misc_reg, val);
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}
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#if FULL_SYSTEM
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Fault hwrei() { return xc->hwrei(); }
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int readIntrFlag() { return xc->readIntrFlag(); }
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void setIntrFlag(int val) { xc->setIntrFlag(val); }
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bool inPalMode() { return xc->inPalMode(); }
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void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
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bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
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#else
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void syscall() { xc->syscall(); }
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#endif
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bool misspeculating() { return xc->misspeculating(); }
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ExecContext *xcBase() { return xc; }
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};
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#endif // __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
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