89ea323250
Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
221 lines
24 KiB
Text
221 lines
24 KiB
Text
|
|
---------- Begin Simulation Statistics ----------
|
|
host_inst_rate 344098 # Simulator instruction rate (inst/s)
|
|
host_mem_usage 199968 # Number of bytes of host memory used
|
|
host_seconds 0.02 # Real time elapsed on the host
|
|
host_tick_rate 1795121173 # Simulator tick rate (ticks/s)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
sim_insts 6404 # Number of instructions simulated
|
|
sim_seconds 0.000034 # Number of seconds simulated
|
|
sim_ticks 33777000 # Number of ticks simulated
|
|
system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_miss_latency 5320000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 5035000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_miss_latency 4872000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 4611000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks.
|
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_miss_latency 10192000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_miss_latency 9646000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_hits 1868 # number of overall hits
|
|
system.cpu.dcache.overall_miss_latency 10192000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_misses 182 # number of overall misses
|
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_miss_latency 9646000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.dcache.tagsinuse 104.111261 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
|
system.cpu.dtb.accesses 2060 # DTB accesses
|
|
system.cpu.dtb.acv 0 # DTB access violations
|
|
system.cpu.dtb.hits 2050 # DTB hits
|
|
system.cpu.dtb.misses 10 # DTB misses
|
|
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu.dtb.read_hits 1185 # DTB read hits
|
|
system.cpu.dtb.read_misses 7 # DTB read misses
|
|
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_hits 865 # DTB write hits
|
|
system.cpu.dtb.write_misses 3 # DTB write misses
|
|
system.cpu.icache.ReadReq_accesses 6415 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_hits 6136 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_rate 0.043492 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.043492 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks.
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.demand_accesses 6415 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
|
|
system.cpu.icache.demand_hits 6136 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_rate 0.043492 # miss rate for demand accesses
|
|
system.cpu.icache.demand_misses 279 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_rate 0.043492 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_hits 6136 # number of overall hits
|
|
system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_rate 0.043492 # miss rate for overall accesses
|
|
system.cpu.icache.overall_misses 279 # number of overall misses
|
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_rate 0.043492 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.replacements 0 # number of replacements
|
|
system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.tagsinuse 128.649737 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 6136 # Total number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
system.cpu.itb.accesses 6432 # ITB accesses
|
|
system.cpu.itb.acv 0 # ITB acv
|
|
system.cpu.itb.hits 6415 # ITB hits
|
|
system.cpu.itb.misses 17 # ITB misses
|
|
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_miss_latency 3796000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 374 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 19396000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.997326 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 373 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 0.002786 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 23192000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 17840000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.997763 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 23192000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 446 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 17840000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 179.928092 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
system.cpu.numCycles 67554 # number of cpu cycles simulated
|
|
system.cpu.num_insts 6404 # Number of instructions executed
|
|
system.cpu.num_refs 2060 # Number of memory references
|
|
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|